Vendor: OPENEDGES Technology, Inc. Category: Network-On-Chip

High speed NoC (Network On-Chip) Interconnect IP

The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end i…

Contact Provider Request Datasheet

Overview

The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow. It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.

Key features

  • Memory Subsystem IP
    • Tuning the performance for the entire SoC memory subsystem
    • ActiveQoS bandwidth and latency control for the entire SoC memory subsystem
  • ​High-Speed HyperPath Technology
    • More than 1GHz at 28nm processor or more than 800MHz at low power 28nm
  • ​Flexible Floorplan & Physical Design Friendly
    • Long-distance Asynchronous Bridge (LDA) technology solves long and narrow topology design
  • ​Ultra Low Power
    • Enables <200uW idle power for entire backbone (+3M gate size)
  • ​Area (Wire Congestion)
    • Less than 50% of typical AXI-based backbone bus area
  • ​Design Tools
    • End-to-end RTL and verification package generation with ORBIT toolkit

Block Diagram

OIC block diagram

Benefits

  • High Performance
    • Proprietary HyperPath technology enabling 2x performance
    • Extremely low latency with LDA technology
    • Dynamic priority control in OIC and OMC, based on observed latency & bandwidth (ActiveQoS)
  • ​Low Power Consumption
    • Advanced Clocking enables extremely low power
    • Proactively clock-gating
  • ​High Flexibility
    • Automated end-to-end RTL generation with an ORBIT design toolkit
    • Fast & easy SoC design of high-speed and long-distance interconnect
  • ​Safety & Security
    • End-to-end ECC (SECDED) support​
    • End-to-end at-speed BIST

Applications

  • Automotive,
  • Application Processors,
  • Digital Baseband Modems,
  • Set-Top-Box,
  • Digital TV,
  • OTT,
  • Surveillance,
  • IoT,
  • Enterprise SSD Controllers

What’s Included?

  • IP Core RTL
  • Simulation Environment
  • Synthesis, Lint Script
  • Detail Documentation

Specifications

Identity

Part Number
OIC
Vendor
OPENEDGES Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

OPENEDGES Technology, Inc.
HQ: Korea
OPENEDGES is an IP technology provider for Smart Computing enabling Internet of Smart Things. OPENEDGES delivers IPs in two key technology areas in Smart Computing; 1) Artificial Intelligence (Deep Learning) Accelerator and 2) Memory Subsystem IP. For Memory Subsystem, we provide Memory Controller IP (OMC), LPDDR5x/5/4 PHY & High speed Network on-chip interconnect IP (OIC). OPENEDGES is the only IP company providing DDR controller, DDR PHY IP & High speed NoC bus interconnect IP all together. When used together within an SoC, OMC, OPHY and OIC provide significant synergy of higher performance, reduced SoC design efforts and a lot easier post-silicon debugging/tuning. And our Artificial Intelligence Accelerator (ENLIGHT) features higher compute density & low-power consumption through our unique bit-precision optimization technology. ENLIGHT and our Memory system IP gives synergy of high efficiency for performance demanding Artificial Intelligence acceleration task. Our IPs are silicon proven and market proven with many Tier 1 semiconductor companies.
Contact OPENEDGES Technology, Inc.

Learn more about Network-On-Chip IP core

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures

Ensuring Network-on-Chip (NoC) security is crucial to design trustworthy NoC-based System-on-Chip (SoC) architectures. While there are various threats that exploit on-chip communication vulnerabilities, eavesdropping attacks via malicious nodes are among the most common and stealthy. Although encryption can secure packets for confidentiality, it may introduce unacceptable overhead for resource-constrained SoCs.

Why verification matters in network-on-chip (NoC) design

In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Accelerating RISC-V development with network-on-chip IP

In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.

Network-on-chip (NoC) interconnect topologies explained

Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.

Frequently asked questions about NoC IP cores

What is High speed NoC (Network On-Chip) Interconnect IP?

High speed NoC (Network On-Chip) Interconnect IP is a Network-On-Chip IP core from OPENEDGES Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP