Vendor: Synopsys, Inc. Category: Single-Protocol PHY

High Speed Ethernet Quad 10G to 100G PCS

The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…

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Overview

The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a complete set of features that enable users to define an optimized PCS in products across a range of 100G Ethernet applications.

The IP, available in single port or quad port configurations, is designed to be used with the 100G Ethernet MAC IP to deliver a complete system solution. The quad port 100G Ethernet PCS IP can be configured as a 2x100G PCS or a 4x50G/25G/10G PCS interfacing with a 4-lane 56G PHY. The single port IP can be configured as one of 4x25G, 2x50G or 1x100G interfacing with a PHY.

The 100G Ethernet PCS IP offers a comprehensive set of features including 100G scrambler/descrambler, 64b/66b encoder/decoder, multi-lane distribution, alignment marker insertion/striping, block synchronization and gearbox, and clock decoupling FIFOs. The multiplexed Reed-Solomon Forward Error Correction (RS-FEC) function provides different channels at various speeds. The IP implements a CGMII on the application side and four lanes interface to the PHY on the line side.

Key features

  • Compliant with the IEEE 802.3 standard
  • Configurable IP available in single or quad port for speeds from 1G to 100G
  • Designed to be used with Synopsys 100G Ethernet MAC IP for 100G Systems
  • Integration tested with the Synopsys 100G Ethernet MAC IP and Synopsys 56G Ethernet PHY IP
  • Comprehensive deliverables packaged in an IP-XACT compatible .run file
  • Includes Synopsys coreConsultant tool for easy configuration
  • Silicon proven

Block Diagram

dwc_ether_hse_quad_100gpcs block diagram

Specifications

Identity

Part Number
dwc_ether_hse_quad_100gpcs
Vendor
Synopsys, Inc.
Type
Silicon IP

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
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Frequently asked questions about Single-Protocol PHY IP

What is High Speed Ethernet Quad 10G to 100G PCS?

High Speed Ethernet Quad 10G to 100G PCS is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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