Vendor: Granite SemiCom Inc. Category: PLL

High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS

Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fr…

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TSMC 40nm G View all specifications

Overview

Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fractional-N division capability. It has been realized in TSMC's 40G technology, does not require off-chip components, is highly reconfigurable, and has very good jitter performance (with on-chip accummulated jitter measurement). It is high speed, can be programmed over a wide range (guaranteed 0.5-7.5 GHz output), is low in power (32 mW at 5GHz), requires only a minimal silicon area, and includes an output driver capable of driving off-chip into 50 ohms at full-speed. Since most of the high-speed circuitry is digital, it is also readily customizable and portable to other technologies.

Key features

  • Wide range and programmability (0.5GHz to 7.5GHz)
  • Predictability
  • Easy Porting
  • Size (0.11mm^2)
  • Power (32mW at 5Ghz)
  • Jitter (1.6ps accummulated at 5Ghz)
  • Testing (on chip process monitoring, lock detect, and accummulated jitter measurement)
  • Temperature Stability
  • Fast Locking

Files

Product Sheet Download

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Silicon Options

Foundry Node Process Maturity
TSMC 40nm G —

Specifications

Identity

Part Number
HSDPLL-V100
Vendor
Granite SemiCom Inc.
Type
Silicon IP

Provider

Granite SemiCom Inc.
HQ: Canada
GSC is focusing on being The Preferred Design House for sub-micron CMOS analog/mixed-mode IP blocks. Next generation mixed-mode design techniques, emphasizing digital signal processing, digital programmability, calibration and trimming, supply-regulation, and testability, are used extensively. GSC has enabling capabilities for extending battery life in intermittent-operation applications.
Contact Granite SemiCom Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS?

High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS is a PLL IP core from Granite SemiCom Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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