Vendor: Orca Systems Inc. Category: PLL

2.4GHz ISM Band ADPLL

The Orca Systems™ ORC9010 is a synthesized or synthesizable low-power all-digital phase-locked loop (ADPLL) Digital IP designed f…

Contact Provider Request Datasheet

Overview

The Orca Systems™ ORC9010 is a synthesized or synthesizable low-power all-digital phase-locked loop (ADPLL) Digital IP designed for 2.4GHz ISM band IoT applications such as Bluetooth and satellite IoT. The IP is portable across semiconductor process nodes and can be optimized for various applications and for various carrier frequencies and modulations. The ADPLL digital IP is designed to integrate with customer provided LC-based digitally controlled oscillator (DCO), time-to-digital-convertor (TDC) and digital-to- time-convertor (DTC).

Key features

  • 2.4 GHz ISM band ADPLL (sub-GHz and L-band IPs also available)
  • 16 MHz to 48 MHz CPU programmable reference frequency
  • Support for 4 DCO Capacitor Banks:
    • PVT (with lock indication, calibration)
    • ACQ (with lock indication, calibration)
    • TRK (with lock indication, calibration, and gear-shifting)
    • MOD (with calibration)
  • Configurable interface from TDC
  • Bluetooth radio channel hopping FSM (Optional)
    • Store/Retrieve calibration data and FCW per channel for
    • frequency/channel hopping
  • CPU Control Interface
  • FCW input to DCO with sub-0.1Hz resolution
  • Loop control:
    • FCW integer and fractional input
    • Modulation Input (two-point)
    • Loop Filter parameter input
  • Initial Calibration FSM:
    • PVT, ACQ, TRK, and MOD Capacitor Bank states & calibration
    • Fine control over ADPLL functions per state
    • Control of timers per state
    • Filter BW control per state
  • Tx and Rx Warmup Calibration FSMs:
    • Including invKdtc, invKtdc, and invKdco calibration
  • Companion Polar Transmitter IP (optional)

Applications

  • Bluetooth
  • Satellite IoT
  • Cellular IoT

What’s Included?

  • Licensed as fully synthesized IPs
  • Optionally Licensed as synthesizable Verilog RTL
  • Full Documentation
  • Basic support provided for customer application
  • Design customization support available
  • C++ binary simulation environment available for system level simulation and bit-exact matching of the RTL with C++ models
  • Extended support available for DCO/TDC/DTC integration

Specifications

Identity

Part Number
ORC9010
Vendor
Orca Systems Inc.
Type
Silicon IP

Provider

Orca Systems Inc.
HQ: USA
Orca Sytems is an RF semiconductor company offering groundbreaking low-power digital transceivers for the growing IoT device market. Our silicon-proven Orca Live Wireless RF™ digital radio and digital power amplifier technology delivers the long promised benefits of digital RF solutions: ultra-low power, low cost, small size and easy integration into system-on-chip (SoC) solutions. Only Orca offers customers a low-power digital RF transceiver portfolio for all major IoT standards, Bluetooth, Wi-Fi and LTE. Orca offers RF transceivers as IP, known good die (KGD) or packaged chips. Orca Live Wireless RF™ digital technology solves three longstanding problems for RF transceivers: 1. Power: Extend the battery life of devices by implementing extremely efficient digital technology in the transceiver’s core components 2. Size: Easily port and integrate RF into SoCs at low process geometries and low voltage 3. Cost: Manufacture digital RF for the leading IoT communication standards in standard CMOS Much more can be found at our website: • Home page: http://www.orcasystems.com/ • About Orca and our technology: http://www.orcasystems.com/about/
Contact Orca Systems Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 2.4GHz ISM Band ADPLL?

2.4GHz ISM Band ADPLL is a PLL IP core from Orca Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP