How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Innosilicon Technology Ltd
Category:
DDR
GDDR7 PHY & Controller
The GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode.
Overview
The GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each byte consists of ten DQ signals and one DQE signal, while the GDDR7 also supports NRZ I/O signaling for low-power operation. With a maximum speed of 32 Gbps per pin, The GDDR7 PHY delivers a peak bandwidth of up to 128 GB/s per memory device. Designed for advanced FinFET process nodes, this PHY is optimized for seamless integration into cutting-edge applications.
The comprehensive product portfolio also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and stay ahead in the competitive landscape of high-performance memory solutions.
Key features
- GDDR7 with data rate up to 32Gbps
- Driver strength and ODT auto calibration
- Auto Hardware/Software CA Bus Training, ERR Training, Read/Write Training with FIFO/LFSR mode
- Auto 2D read VREF Training
- Supports Burst length: 16 Symbols (PAM3) or 32 Symbols (NRZ)
- Supports read/write CRC
- Programmable READ and WRITE latency
- Rx DFE for data inputs, with receiver characteristics programmable per pin
- 3 frequency points auto-change
- Supports PHY low power mode with GDDR7 SGRAM in self-refresh sleep mode/hibernate self-refresh sleep mode
- Configurable 4-channel/2-channel mode
- At-Speed BIST loopback, At-Speed/Stuck-At Scan, boundary scan
- Internal high-performance low-jitter PLL
- Per-bit Tx and Rx data phase delay and Vref adjustment
- Tx de-emphasis EQ and Rx DFE EQ to improve signal integrity
- Accommodates Voltage/Temperature timing drift
- 1.35V ±0.0405V or 1.2V ±0.036V supply for I/O interface (VDDQ)
- Pseudo open drain (POD-135 and POD-12) compatible outputs
- Dynamic Read/Write Training with auto-refresh synchronization function
- Dynamic command address timing adjustment using CAOSC
- Optional package/PCB design and SI/PI analysis service
- Supports Micron, Samsung, Hynix memory devices
Block Diagram
GDDR7 PHY & Controller block diagram
Benefits
- Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
- Zero risk with robust ESD architecture
- Extensive EDA tool support for various design and automation flow
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
- Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing
What’s Included?
- Extensive documentation
- Models
- LIB
- LEF
- Place-and-route abstracts
- LVS netlist
- GDSII files
Specifications
Identity
Part Number
GDDR7 PHY & Controller
Vendor
Innosilicon Technology Ltd
Type
Silicon IP
Controller / PHY
Controller + PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
Innosilicon Technology Ltd
HQ:
China
Innosilicon is a world-class one-stop shop of high-speed interface IP and design services with 18 years of history. Having empowered hundreds of well-known customers including Qualcomm, AMD, Microsoft, Amazon, with all major process nodes covered across the world's top 6 foundries (TSMC/Samsung/GF/UMC/Intel/SMIC) from 55nm to 3nm, Innosilicon boasts over 1300 employees and is fully devoted to extending its leadership in delivering advanced IP and ASIC services. Our team offers unique IP such as HBM3E/2E Combo, GDDR7/6X/6 Combo, LPDDR5X/5/4X/4 Combo, DDR5 DIMM support, UCle Chiplet, various High-speed SerDes and HDMI2.1/eDP1.4 Combo, all with standard PHY and controller combinations as well as custom design options. Our outstanding innovation capabilities have been proven in high-performance computing, high-bandwidth memory, automotive, multimedia low-power IoT and other fields. We drastically improve our customer satisfaction and reduce time to market by offering our unique domain specific design platforms and flexible win-win business models.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR IP Hardening - Overview & Advance Tips
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Interface IP
What is GDDR7 PHY & Controller?
GDDR7 PHY & Controller is a DDR IP core from Innosilicon Technology Ltd listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.