How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR5 DFI Synthesizable Transactor
DDR5 DFI Synthesizable Transactor provides a smart way to verify the DDR5 DFI component of a SOC or a ASIC in Emulator or FPGA pl…
Overview
DDR5 DFI Synthesizable Transactor provides a smart way to verify the DDR5 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR5 DFI Synthesizable Transactor is fully compliant with standard DFI 5.0 Specification and provides the following features.
Key features
- Compliant with DFI 5.0 Specification.
- DFI-DDR5 Applies to :
- DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft) Specifications
- Supports all Interface Groups.
- Supports Write Transactions with Data mask/Write DBI.
- Supports Write Transactions with data CRC
- Supports Read Transactions with CRC.
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports Low power control features.
- Supports Error signaling.
- Supports DFI Read/Write Chip Select.
- Supports 3DS Stack.
- Supports Inactive CS.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI 5.0 Specification
Block Diagram
DDR5 DFI Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the DDR5 DFI testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Part Number
DDR5 DFI Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about DDR Interface IP
What is DDR5 DFI Synthesizable Transactor?
DDR5 DFI Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.