Vendor: SmartDV Technologies Category: DDR

DDR4 Assertion IP

DDR4 Assertion IP provides an efficient and smart way to verify the DDR4 designs quickly without a testbench.

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Overview

DDR4 Assertion IP provides an efficient and smart way to verify the DDR4 designs quickly without a testbench. The SmartDV's DDR4 Assertion IP is fully compliant with standard DDR4 Specification.

DDR4 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR4 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports DDR4 memory devices from all leading vendors.
    • Supports 100% of DDR4 protocol standard JESD79-4/JESD79-4A/JESD79-4A_r2 and JESD79-4B_draft.pdf.
    • Supports all the DDR4 commands as per the specs.
    • Supports for following Package Pin out and Addressing,
    • 2GB
    • 4GB
    • 8GB
    • 16GB
    • Supports the following devices.
    • X4
    • X8
    • X16
    • Supports all speed grades as per specification.
    • Quickly validates the implementation of the DDR4 standard JESD79-4/JESD79-4A/JESD79-4A_r2 and JESD79-4B_draft.pdf.
    • Supports Programmable Write latency and Read latency.
    • Supports Programmable burst lengths: 4,8.
    • Supports the following burst types.
    • Sequential
    • Interleave
    • Supports burst order.
    • Checks for following
    • Check-points include power up,initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
    • Supports for all Mode registers programming.
    • Supports for Data Mask and Data Bus Inversion(DBI).
    • Supports for write Leveling for calibrations.
    • Supports for Fine Granularity Refresh Mode.
    • Supports for ZQ Calibration commands.
    • Supports for DQ Vref training
    • Supports for CRC for Write Operations.
    • Supports for DLL features.
    • Supports for Multi purpose Register.
    • Supports for Per Dram Addressability.
    • Supports for CAL Mode Operation.
    • Supports for Command Address Parity features.
    • Supports for Control Gear down mode.
    • Supports for Maximum Power Saving mode.
    • Supports MBIST PPR.
    • Supports for both Synchronous and Asynchronous On-Die Termination modes.
    • Supports for Power Down features.
    • Supports for input clock stop and frequency change.
    • Supports for full-timing as well as behavioral versions in one model.
    • Supports for all timing delay ranges in one model: min, typical and max.
    • Constantly monitors DDR4 behavior during simulation.
    • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV DDR4 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure DDR4 Assertion IP functionality.

Block Diagram

DDR4 AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
DDR4 AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is DDR4 Assertion IP?

DDR4 Assertion IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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