Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)
The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrate…
- UMC
- 40nm
- ULP
- Available on request
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)
The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrate…
UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 90nm LL/RVT MPCA core cell library
UMC 90nm LL/RVT MPCA core cell library
UMC 0.18um Generic process MPCA core cell library
UMC 0.18um Generic process MPCA core cell library
UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)
UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)
UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)
UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)
UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)
UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60).
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library
UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library
UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library
UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)