MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
- SMIC
- 40nm
- Available on request
MIPI PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare MIPI PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
MIPI D-PHY Rx-Only 2 Lanes in SMIC (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
MIPI D-PHY Bidirectional 4 Lanes in SMIC (40nm, 28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
MIPI D-PHY Bidirectional 2 Lanes in SMIC (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
1.5G MIPI D-PHY in SMIC 130nm~28nm
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
MIPI D-PHY Tx IP, Silicon Proven in SMIC 55LL
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.
MIPI D-PHY Rx IP, Silicon Proven in SMIC 55LL
The D-PHY specification, version 1.2, is perfectly complied with by the MIPI D-PHY Analog RX IP Core.
MIPI DPHY Gen2 Rx-Only 4 Lanes - SMIC 40LL 2.5V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Rx-Only 2 Lanes - SMIC 40LL 2.5V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Bidirectional 4 Lanes - SMIC 40LL 2.5V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Bidirectional 2 Lanes - SMIC 40LL 2.5V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI MPHY v3.1, 1Tx-1Rx Type-1, SMIC 40LL, N/S orientation
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applicat…
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1”, which consists of Bi-directional 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.