This IP is a programmable Analog PLL suitable for high speed clock generation.
- SMIC
- 130nm
- G
PLL IP cores (Phase-Locked Loop IP) are essential components in modern SoC, ASIC, and mixed-signal designs, enabling precise clock generation, frequency synthesis, and jitter reduction.
Phase-locked loop IP is widely used in applications such as high-speed interfaces (SerDes, PCIe, Ethernet), wireless communication, processors, and clock distribution networks.
This page allows you to compare PLL IP cores from leading vendors by frequency range, jitter performance, power consumption, process node compatibility, and supported use cases.
Whether you need a low-power PLL for IoT or a high-performance low-jitter PLL for high-speed data links, you can quickly identify the most suitable solution for your design.
This IP is a programmable Analog PLL suitable for high speed clock generation.
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control …
This PLL is designed for audio clock generation.
SMIC 0.13um 1.2v / 3.3v Audio PLL
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 0.18um 1.8v APLL with Free Running
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for generating system clock.
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for generating system clock.
SMIC 0.13um 1.2v/3.3v PLL Specification
This PLL is designed for audio clock generation.
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
The present IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for system clock generation.
This IP is a fixed divider Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This PLL is designed for audio clock generation.
This PLL is designed for audio clock generation.