Phase-locked loop system 2.8 to 3.3 GHz
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…
- SMIC
- 180nm
- G
- Silicon Proven
PLL IP cores (Phase-Locked Loop IP) are essential components in modern SoC, ASIC, and mixed-signal designs, enabling precise clock generation, frequency synthesis, and jitter reduction.
Phase-locked loop IP is widely used in applications such as high-speed interfaces (SerDes, PCIe, Ethernet), wireless communication, processors, and clock distribution networks.
This page allows you to compare PLL IP cores from leading vendors by frequency range, jitter performance, power consumption, process node compatibility, and supported use cases.
Whether you need a low-power PLL for IoT or a high-performance low-jitter PLL for high-speed data links, you can quickly identify the most suitable solution for your design.
Phase-locked loop system 2.8 to 3.3 GHz
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…
40-450MHz Programmable Clock Generator PLL, SMIC0.13um
The AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz.
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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily ret…
Analog PLL suitable for high speed clock generation.
Analog PLL suitable for high speed clock generation.
Analog PLL suitable for high speed clock generation.
A programmable analog PLL suitable for high speed clock generation.
50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
Integer-N PLL, 600M-2.4G on SMIC 40nm
This present IP is a self-biased Phase Locked Loop (PLL) circuit, which can cover 600MHz-2.4GHz vco output frequency.
This IP is a programmable Analog PLL suitable for low frequency reference clock and large feedback clock divider.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 65nm 1.2v/2.5v Spread Spectrum PLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.