Flash Memory LDPC
LDPC corrects errors caused by flash storage failure mechanisms.
Overview
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while reading from the storage devices. Decoding corrects read errors. The LDPC code that is used with storage devices should exhibit a very low error floor (very low BER) and have high throughput.
Key features
- Irregular parity check matrix
- Layered decoding
- Minimum sum algorithm
- Soft decision decoding
- BCH decoder corrects up to t errors where t = 10 or 12
- ETSI EN 755 V1.4.1 compliant
Applications
- Flash Memory
What’s Included?
- System Matlab model
- Synthesizable Verilog RTL
- Test Benches for verification
- Documentation
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about Channel Coding IP cores
What is Flash Memory LDPC?
Flash Memory LDPC is a Channel Coding IP core from T2M GmbH listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.