Vendor: EnSilica Category: Channel Coding

Ultra Low-power, compact Hybrid Viterbi Decoder

This IP core is available with a configurable number of ACS units to suit a range of throughput requirements.

Contact Provider Request Datasheet

Overview

This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 ACS units. The configurations with 1, 2, 4, 8 and 16 ACS units decode a message bit in 33, 17, 9, 5 and 3 clock cycles respectively. By implementing a register exchange traceback algorithm this core is suitable for applications with strict latency constraints. In particular the latency is equal to the traceback length. The regsiter exchange algorithm doesn’t require any RAM memory for storage.
The core can be used for streaming or packetised data applications. By using signed LLR input data it naturally supports de-puncturing by inserting zeros. The core provides automatic normalization of the path metrics, ensuring that overflow cannot occur.

Key features

  • Constraint length 7.
  • Generator polynomials g0 = 1338 g1 =1718.
  • Register exchange traceback from best state.
  • Optional trellis end state for packetised data.
  • Optional trellis start state for packetised data.
  • Low latency equal to block length.
  • Signed 3-bit soft decision (LLR) inputs.
  • De-puncturing support.
  • Automatic normalization.
  • Configurable number of ACS units.
  • Parameterisable soft core

Benefits

  • Low Silicon area
  • No memories
  • Easy to optimise for the end application by configuring number of ACS units
  • Low latency provided by register exchange traceback with fast flush
  • Improved performance through best state determination
  • Low gate count and area :
    • Configuration: 3-bit soft decision, 35-bit traceback, 8 ACS units on

Applications

  • Hearing Aids
  • Connected audio
  • OFDM systems - WiFi, DVB, DAB

What’s Included?

  • RTL
  • Testbench
  • Synthesis scripts
  • Documentation
  • MATLAB and C++ bit exact mode

Specifications

Identity

Part Number
eSi-Viterbi-LP
Vendor
EnSilica

Provider

EnSilica
HQ: UK
EnSilica is a leading fabless design house focused on custom ASIC design and supply for OEMs and system houses, and IC design services for companies with their own design teams. The company has world-class expertise in supplying custom analog, mixed signal and digital IC’s to its international customers in the automotive, industrial, healthcare and consumer markets. The company also offers a broad portfolio of core IP covering cryptography, Radar and communications systems. EnSilica has a track record in delivering high quality solutions to demanding industry standards.
Contact EnSilica

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is Ultra Low-power, compact Hybrid Viterbi Decoder?

Ultra Low-power, compact Hybrid Viterbi Decoder is a Channel Coding IP core from EnSilica listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP