Vendor: SmartDV Technologies Category: Ethernet

Ethernet 10GBase-KR Synthesizable Transactor

The Ethernet 10GBase-KR Synthesizable Transactor verifies Ethernet interfaces.

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Overview

The Ethernet 10GBase-KR Synthesizable Transactor verifies Ethernet interfaces. Ethernet is build on top of it to make it robust. Ethernet 10GBase-KR Synthesizable Transactor provides a smart way to verify the Ethernet component of a SOC or a ASIC in Emulator or FPGA platform. Ethernet 10GBase-KR Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key features

  • Supports 10G as per 802.3:
    • Supports XGMII
    • Supports XTBI (i.e Output of 8b/10b PCS)
    • Supports 10GBASE-KR with scrambler
    • Supports FEC for 10GBase-KR
    • Supports scrambler
    • Supports backplane auto-negotiation for 10GBase-KX4 and 10GBase-KR
  • Supports Mac control and data frames support
  • Ability to generate VLAN tagged and Priority tagged frames
  • Supports Pause frame detection and generation
  • Supports Jumbo frames
  • Supports Under and oversize frame
  • PCS to serdes interface supports all widths
  • Full support for IEEE 1588-2002 and IEEE 1588-2008
  • Supports all types of TX and RX errors insertion/detection at each layer
    • Supports Under and oversize frame
    • CRC errors
    • Framing errors
    • Pause frame errors
    • Disparity and Auto-negotiation errors
    • Invalid code group insertion
    • Invalid /K/ characters insertion
    • Lane Skew insertion
    • Invalid AN sequence error insertion
    • Missing /K/ characters for packet boundaries
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

Ethernet 10GBase-KR Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the Ethernet testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Ethernet 10GBase-KR Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about Ethernet IP cores

What is Ethernet 10GBase-KR Synthesizable Transactor?

Ethernet 10GBase-KR Synthesizable Transactor is a Ethernet IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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