Vendor: Key ASIC Category: Single-Protocol PHY

Ethernet 10/100 PHY

The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface).

Contact Provider Request Datasheet

Overview

The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface). It implements all 10/100M Ethernet Physical- layer functions including the Physical Coding Sub-layer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent sub-layer (TP-PMD), 10Base-Tx Encoder/Decoder, and Twisted Pair Media Access Unit (TPMAU).

 

Key features

  • Supports MII.
  • Auto-MDX
  • 10/100Mbs operation supported
  • Full/half duplex operation
  • Twisted pair output only
  • Supports Base Line Wander (BLW) compensation
  • Adaptive Equalization
  • 25MHz crystal/oscillator as clock source
  • IEEE 802.3/802.3u compliant including auto- negotiation
  • 0~125°C junction temperature
  • Silterra 130nm CMOS process

Block Diagram

KA13ETHB33 block diagram

Benefits

  • With on-chip DSP (Digital Signal Processing) technology, the chip provides excellent performance under all operating conditions.

Applications

  • Network Interface Adapters
  • Ethernet Hubs/Switches
  • ADSL/Cable Modems
  • VoIP Phone Sets

What’s Included?

  • Data Sheet
  • Test Documentation
  • Integration Guide
  • GDSII
  • LVS netlist
  • LEF model
  • Verilog Model
  • Timing Model

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
KA13ETHB33
Vendor
Key ASIC
Type
Silicon IP

Provider

Key ASIC
HQ: Malaysia
Key ASIC was incorporated in the year 2005. In 2006, we were awarded Multimedia Super Corridor (MSC) Status by the Malaysia Digital Economy Corporation (MDEC). We started with the design of IP, ASIC, and SoC. In 2009, we were listed on the main board of KLSE. Khazanah and CIMB are our main investors. Key ASIC is not only a leading ASIC / SoC design service company, we are also a turnkey service company from spec-in to system module that focuses on AI chips, IoT, and medical applications. We are committed to providing customers with competitive SoC professional one-stop design services in terms of PPA (Performance, Power, and Area). Based in Kuala Lumpur, Malaysia with R&D Centers in Malaysia and Tai Yuen Hi-Tech Industrial Park Taiwan, Key ASIC provides ODM and OEM of ASIC design services from Specification, RTL, Netlist to silicon, as well as process migration from GDSII. Our experienced SoC designer and engineers combined with extensive manufacturing, logistics resources, and a flexible engagement model can provide Key ASIC customers with a comprehensive support system for modular ASIC innovation from IP development through prototype to production.
Contact Key ASIC

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is Ethernet 10/100 PHY?

Ethernet 10/100 PHY is a Single-Protocol PHY IP core from Key ASIC listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP