Vendor: Zero ASIC Category: eFPGA

eFPGA on GlobalFoundries GF12LP

All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee.

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GlobalFoundries 12nm LP View all specifications

Overview

All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.

Parametrized soft RTL logic wrap the hardened IP core to handle reset, boot-up, security, and bitstream loading. Bitstream programming is done via a standardize memory mapped register interfaces (APB, AXI-Lite, or UMI) selectable by the user during design integration.

The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process. The picture below shows the full layout (GDS) of an integration ready Z1000 eFPGA core.

Process LUTs Regs I/O DSPs BRAM Width Height
GF12LP 2,048 2,048 1,024 0 0 1036.8um 1037.2um

Block Diagram

Z1000-GF12LP block diagram

Benefits

  • 100% open and standardized FPGA architectures
  • 100% open source FPGA bitstream formats
  • 100% open source FPGA development tools

Applications

  • FPGA/CPLD/ASIC obsolescence
  • hardware security
  • I/O peripherals
  • interface bridges
  • motor control
  • signal muxing
  • power management
  • glue logic

 

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP —

Specifications

Identity

Part Number
Z1000-GF12LP
Vendor
Zero ASIC
Type
Silicon IP

Provider

Zero ASIC
HQ: USA
Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon.
Contact Zero ASIC

Learn more about eFPGA IP core

Tapeout Predictability with Hardened eFPGA IP Blocks

For architects, adding flexibility via embedded FPGA (eFPGA) is a natural solution for post-silicon requirements, allowing for evolving standards and late-breaking feature additions. However, a critical question remains: Does adding programmable logic help your schedule, or does it introduce a new layer of uncertainty and risk? The answer lies in the delivery format. While soft IP offers configuration flexibility, hardened eFPGA IP blocks are the secret weapon for teams prioritizing tapeout predictability.

Accreditation Without Compromise: Making eFPGA Assurable for Decades

For embedded FPGA (eFPGA) to succeed in defense, we must change the narrative. It cannot be treated as a hobbyist FPGA dropped into an SoC. It must be treated as an assured ASIC IP block governed by disciplined processes, verifiable artifacts, and increasingly by open-source toolchains that guarantee long-term independence.

Silicon Insurance: Why eFPGA is Cheaper Than a Respin

This blog reframes the “flexibility vs. cost” debate in modern SoC design, positioning eFPGA not as a luxury feature, but as a critical financial hedge against the rising costs of advanced silicon nodes.

Integrating eFPGA for Hybrid Signal Processing Architectures

As system requirements evolve toward multi-standard, reconfigurable platforms, signal processing architectures are under pressure to deliver both ASIC-class performance and software-like flexibility. Semiconductor engineers face a fundamental tradeoff: fixed logic yields, unmatched throughput, and efficiency, but cannot adapt once taped out. Software-programmable solutions offer flexibility but often miss hard real-time performance constraints and can consume more power.

Frequently asked questions about eFPGA IP cores

What is eFPGA on GlobalFoundries GF12LP?

eFPGA on GlobalFoundries GF12LP is a eFPGA IP core from Zero ASIC listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this eFPGA?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this eFPGA IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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