Vendor: Eliyan Category: Custom

Die-to-Die PHY

The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and…

Overview

The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and are available on both standard and advanced packaging.

The vendor uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging types (including advanced packaging and standard packaging).

For Standard Packaging, the vendor has a family of high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same standard organic/laminate package substrate. The PHY technologies with patented implementation techniques enable the same levels of performance and power as those provided by advanced packaging options, while providing benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry standard packaging. In many applications this eliminates the need for advanced packaging technologies such as silicon interposers or silicon bridges.

Block Diagram

Applications

  • Chiplets connected on standard organic packages without large silicon interposers or silicon bridges but with interposer-like bandwidth/power/latency.
  • SiP applications that benefit from up to at least four times the substrate area compared to the largest silicon interposer and thus a far higher number of chiplets in the package, resulting in major performance and power advantages.
  • ASIC designs where a Network on Chip is split across two or more chiplets.
  • Applications that benefit from placement flexibility to mix and match chiplets of different dimensions.
  • Chiplet applications–such as HBM—where there must be physical separation between a hot ASIC and heat-sensitive dies.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
NuLink
Vendor
Eliyan
Type
Silicon IP

Provider

Eliyan
HQ: USA
Eliyan Corporation is leading the chiplet revolution, focusing on a fundamental challenge with scaling semiconductor performance, size, power, and cost to meet the needs of high-performance computing applications, from desktop to datacenter. It has developed a breakthrough method to enable the industry’s highest performing interconnect for homogenous and heterogenous multi-die architectures using standard packaging substrates, enabling increased sustainability through reduction in costs, manufacturing waste and power consumption. The company’s Bunch of Wires (BoW) technique, invented by founder Ramin Farjadrad and proven to increase performance by 2x and reduce power in half in advanced process technologies, provides a more efficient approach to developing chiplet-based architectures – which are the pathway to the continued scaling of Moore’s Law.

Learn more about Custom IP core

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings

The growing adoption of RISC-V in high-performance and scientific computing has increased the need for performance-portable code targeting the RISC-V Vector (RVV) extension. However, current compiler infrastructures provide limited end-to-end support for generating optimized RVV code from high-level representations to low-level implementations. In particular, existing MLIR distributions lack practical lowering paths that map high-level abstractions to RVV intrinsics, limiting their applicability for production-ready RISC-V kernels. This paper presents a compilation approach that combines MLIR with xDSL to bridge the missing lowering stages required for RVV code generation.

RISC-V basics: The truth about custom extensions

The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), edge computing, automotive, and industrial markets continue to expand, they are driving a fundamental shift in processor design.

Frequently asked questions about Custom Die-to-Die IP cores

What is Die-to-Die PHY?

Die-to-Die PHY is a Custom IP core from Eliyan listed on Semi IP Hub.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP