DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM devi…
Overview
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM.
Key features
- Compatible with JESD79-4B and JESD209-4B
- Combined the DDR4 and LPDDR4 interface
- Data Rate:
- DDR4: Up to 3200 Mbps
- LPDDR4: Up to 3200 Mbps
- Support loopback test
- Support VREFE for VREFCA of DDR4 device
- Support VREFI for internal DQ receiver
- Support retain the IO output
- Programmable On Die Termination:
- DDR4: 240/120/80/60/48/40/34 Ω
- LPDDR4: 240/120/80/60/48/40 Ω
- Support weak driver
- Block cell includes Local Decap
- Process Node: TSMC 22nm
- Operation Temperature: Tj = -40℃ ~ +125℃
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 22nm | ULL | — |
Specifications
Identity
Provider
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Frequently asked questions about High-Speed I/O Pad IP
What is DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm?
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm is a High-Speed IP core from UniIC listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this High-Speed?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.