Vendor: Agile Analog Category: Mixed Signal Subsystem

Sensor Interface Subsystem

The agileSensorIF Subsystem is an efficient and integrated sensor interface for SoCs/ASICs.

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Overview

The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs. Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF). The agileSensorIF Subsystem enables easy interaction with the analog world.  

The components within the subsystem can be customized to suit a variety of applications. This includes selecting the number of agileADC, agileDAC, and agileCMP_LP blocks, as well as their bit depth and sample rate. This allows the agileSensorIF Subsystem to be perfectly tailored to your exact needs and use case.

Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance. The monitoring of process, voltage and temperature variations are critical to optimize power and performance for modern SoCs/ASICs, especially for advanced node and FinFET processes.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key features

  • agileADC
    • Resolution: up to 12-bits
    • Sampling Rate (Fs)1: up to 64 MSPS
    • SNR1: Typ 70 dB
    • ENOB1: Typ 11.3 bits
    • SFDR1: Typ 90 dBc
    • INL: +/2 LSB
    • DNL: +/-1 LSB
    • Up to 16 input channels
  • agileDAC
    • Resolution: up to 12-bits
    • Sampling Rate (Fs)1: up to 20 MSPS
    • SNR1: Typ 70 dB
    • INL: +/2 LSB
    • DNL: +/-1 LSB
  • agileCMP
    • Programmable Thresholds
    • Active Current: 1.5uA (max)
    • Detection Time: 2μs (typical)
    • Hysteresis: 20mV
    • Threshold Step Size: 56.25mV
    • Threshold Accuracy: 10mV

Block Diagram

agileSensorIF block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
agileSensorIF
Vendor
Agile Analog
Type
Silicon IP

Provider

Agile Analog
HQ: United Kingdom
Agile Analog is transforming the world of analog IP with Composa™, its innovative, configurable, multi-process analog IP technology. Headquartered in Cambridge, UK, with a growing number of partners and customers across the globe, Agile Analog has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications on almost any process from any foundry. The company provides a wide and ever expanding selection of analog IP and subsystems for power management, data conversion, IC health and monitoring, security and always-on domains. Agile Analog's novel approach utilises tried and tested analog circuits within its Composa library to create customised and verified analog IP solutions. This reduces the time to market and increases quality, helping to accelerate innovation in semiconductor design.
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Frequently asked questions about Mixed-Signal Subsystem IP cores

What is Sensor Interface Subsystem?

Sensor Interface Subsystem is a Mixed Signal Subsystem IP core from Agile Analog listed on Semi IP Hub.

How should engineers evaluate this Mixed Signal Subsystem?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Mixed Signal Subsystem IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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