MIPI CSI2 Transceiver
The Foresys MIPI CSI2 Tx Core provides a fast path to integrating Image Sensors into a wide variety of products based on Altera d…
Overview
The Foresys MIPI CSI2 Tx Core provides a fast path to integrating Image Sensors into a wide variety of products based on Altera devices. It is designed to convert an internal payload agnostic Avalon Streaming data bus to MIPI/CSI2 data.
Key features
- Provides Compatible MIPI D-Phy v1.1 physical layer using FPGA LVDS/LVCMOS IO and passive network
- Supports CSI-2 protocol for unidirectional data transfer
- Compatible with D-PHY Configured for 1 clock and 1 data lane
- Intended for per-lane clocks rates up to 1 Gbps, depending on device speed grade
- Generates single logical channel CSI-2 encapsulation, including:
- CSI-2 short packets [SOF,EOF,SOL,EOL]
- CSI-2 header and ECC field
- CSI-2 data CRC
- Transmits MIPI Packets including: LP to HS state transition, sync pattern, payload, and trailer
Block Diagram
Files
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Specifications
Identity
Provider
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Frequently asked questions about MIPI IP cores
What is MIPI CSI2 Transceiver?
MIPI CSI2 Transceiver is a MIPI IP core from Foresys listed on Semi IP Hub.
How should engineers evaluate this MIPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.