Compact High-Speed 64-bit CPU Core

Overview

AndesCore™ NX25F is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs to access address space over 4GB. NX25F also supports single- and double-precision floating point instructions. NX25F comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, ECC for L1 memory soft error protection, and Andes Custom Extension™ (ACE) to add proprietary instructions to accelerate performance/power consumption critical spots.

NX25F's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap™ and WFI mode for low power and power management, and JTAG debug interface for development support.

Key Features

  • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
  • Floating point extension
  • Andes extensions, architected for performance and functionality enhancements
  • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
  • 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
  • 16/32-bit mixable instruction format for compacting code density
  • Branch predication to speed up control code
  • Return Address Stack (RAS) to speed up procedure returns
  • Physical Memory Protection (PMP)
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
  • Enhancement of vectored interrupt handling for real-time performance
  • Advanced CoDense™ technology to reduce program code size

Benefits

  • Performance
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extension
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    • 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
    • 16/32-bit mixable instruction format for compacting code density
    • Branch predication to speed up control code
    • Return Address Stack (RAS) to speed up procedure returns
    • Physical Memory Protection (PMP)
    • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
    • Enhancement of vectored interrupt handling for real-time performance
    • Advanced CoDense™ technology to reduce program code size
  • Flexibility
    • Easy arrangement of preemptive interrupts
    • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
    • ECC or Parity check on level-one memories for fault protection
    • Several configurations to tradeoff between core size and performance requirements
  • Power Management
    • PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions

Block Diagram

Compact High-Speed 64-bit CPU Core Block Diagram

Applications

  • Large-scale network controllers
  • High capacity storage devices
  • Data analytic accelerators
  • Computer Vision and Pattern Recognition
  • Artificial Intelligence to Deep Learning

Deliverables

  • NX25F with CPU Subsystem
    • Pre-integrated NX25F, PLIC, Debug Module and simulation-only encrypted Platform
  • NX25F with AE350 Platform
    • NX25F with CPU Subsystem, plus AXI/AHB Platform

Technical Specifications

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Semiconductor IP