400G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media and data streaming with speeds up to 400Gbps in ASICs even in processor-less SoC designs.

Trouble-free network operation is ensured through run-time programmability of all required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Protocol (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN.

The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or optionally via registers mapped on an SoC bus. Up to 32 streaming interfaces are used to transmit data, and up to 32 to receive data. Such each pair of receive and transmit interfaces (a “channel”) is configured independently, with the source UDP port, destination IP address and UDP port, multicast receive address, and transmit mode (unicast or multicast). The AMBA® AXI4-stream or the Avalon®-ST streaming protocols and the AMBA AHB and AXI, Avalon-MM, or Wishbone SoC bus protocols are supported.

Complete UDP/IP Hardware Stack

• 40G, 50G, 100G and 400G Ethernet
• IPv4 support with packet fragmentation
• Jumbo and Super Jumbo Frames
• Transmit and Receive
• ARP with Cache
• ICMP (Ping Reply)
• IGMPv3 (Multicast)
• UDP/IP Unicast and Multicast
• UDP Port Filtering
• UDP/IP Checksums generation and validation, and Ethernet CRC validation
• VLAN (IEEE 802.1Q) support
• 1 to 32 UDP transmit and 1 to 32 UDP receive channels – core size doesn’t grow linearly with the channel count
• Ethernet Framing processing for non-UDP user-provided packets
• DHCP client

Trouble-Free Operation

• Run-time programmable network parameters
  • Local MAC address, Local IP address, Gateway address, and IP subnet mask
  • Per-channel: Destination IP address, Source and Destination UDP ports, multicast enable/disable and receive group
• ARP support for operation in networks with Dynamic IP allocation

Easy SoC Integration

• Flexible interfaces:
  • Packet Data: 512-bit streaming capable using Avalon-ST or AXI4-Stream
  • Control/Status Registers: Generic 32-bit SRAM-like, or optionally 32-bit AHB, AXI, Avalon-MM or Wishbone
• Separate clock domains for packet processing and control/status interfaces
• Configurable buffer sizes
• Rich interrupt support for system events

The UDPIP-400G core is well suited for ultra-high-bandwidth, low-latency, and deterministic Ethernet networking applications, including:

• Data centers and cloud infrastructure
• AI training, inference, and accelerator fabrics
• High Performance Computing (HPC)
• Storage servers and NVMe-based systems
• Smart NICs
• Radar, sensor fusion, and real-time data acquisition
• Backbone networks
• High-frequency trading systems
• Media streaming and broadcasting
• Server-to-server interconnects
• Remote telemetry
• Control for industrial and scientific systems

• The core is available in synthesizable RTL and encrypted RTL forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts, and comprehensive user documentation.