Vendor: SmartDV Technologies Category: CPRI

CPRI Synthesizable Transactor

CPRI Synthesizable Transactor provides a smart way to verify the CPRI component of a SOC or a ASIC in Emulator or FPGA platform.

Contact Provider Request Datasheet

Overview

CPRI Synthesizable Transactor provides a smart way to verify the CPRI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's CPRI Synthesizable Transactor is fully compliant with standard CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0 and provides the following features.

Key features

  • Compliant with CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0.
  • Supports complete CPRI Tx/Rx functionality.
  • Supports the Physical link layer (Layer 1) of the CPRI specification.
  • Supports different standard line bit rates of the CPRI specification
    • 614.4 MBPS
    • 1228.8 MBPS
    • 2457.6 MBPS
    • 3072.0 MBPS
    • 4915.2 MBPS
    • 6144.0 MBPS
    • 8110.08 MBPS
    • 9830.4 MBPS
    • 10137.6 MBPS
    • 12165.12 MBPS
    • 24330.24 MBPS
  • Supports scrambler as in CPRI specification with enabling and disabling.
  • Supports insertion of scrambler errors.
  • Support disparity and invalid code insertion in 8B/10B.
  • Supports 8B/10B line coding for bit rates upto 9830.4.
  • Supports 64B/66B line coding without RS-FEC for 8110.08, 10137.6, 12165.12 and
  • 24330.24 bit
  • Supports 64B/66B line coding with RS-FEC for 24330.24 bit rate
    • RS-FEC with alignment marker and without scrambler support
    • RS-FEC without alignment marker and with scrambler support
    • RS-FEC without alignment marker and without scrambler support
  • Performs CPRI Hyperframe Framing
    • Performs interleaving of IQ data, sync, C&M data, and vendor specific information
    • Provides an 8-bit, 16-bit, or 32-bit for IQ data
  • Performs sub channel mapping:
    • Supports a slow C&M channel based on a serial HDLC interface for following standard HDLC bit rates
  • - 240 KBPS
  • - 480 KBPS
  • - 960 KBPS
  • - 1920 KBPS
  • - 2400 KBPS
  • - 3840 KBPS
  • - 4800 KBPS
  • - 7680 KBPS
  • - HDLC bit rate negotiated on higher layer
    • Supports a fast C&M channel based on a serial Ethernet interface
  • Performs synchronization and timing.
  • Supports the L1 Inband Protocol.
  • Provides a parallel interface for merging vendor specific data into the CPRI frame.
  • Provides a start-up sequence state machine in hardware for both REC and RE nodes
  • which performs:
    • L1 Synchronization
    • Protocol setup
    • C&M Plane setup
  • Supports Link Maintenance
    • LOS detection
    • LOF detection
    • RAI indication
    • SDI indication
  • Detects and reports the following errors
    • Invalid control character
    • Invalid data character
    • Invalid 10bit code
    • Scrambler errors
    • Disparity errors
    • Time division multiplexing errors
    • Under and oversize frame
    • CRC errors
    • Framing errors
    • LOS and LOF error injection
    • Block sync bits error
    • Block encoding error
    • RS-FEC alignment marker error
    • RS-FEC parity error
  • Supports glitch insertion and detection
  • Supports bus accurate timing and timing checks

Block Diagram

CPRI Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the CPRI testcases
  • Examples showing how to connect and usage of Synthesiable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
CPRI Transactor
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about CPRI IP core

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.

O-RAN Fronthaul Security using MACsec

With 5G being deployed for time-sensitive applications, security is becoming an important consideration. At the same time, Open Radio Access Networks (RAN) are gaining more interest from mobile carriers and governments. Yet, Open RAN networks have serious security challenges, especially in the RAN fronthaul where there are strict timing requirements. This paper proposes MACsec as an efficient data link layer security solution that can assist in meeting these challenges.

Seize the Ethernet TSN Opportunity

The following sections will take a look at the major Ethernet performance issues and how the extensions address those shortcomings. This will be followed by an overview of the applications of TSN for 5G, industrial automation, automotive invehicle communications and avionics. The paper will conclude with a description of Ethernet TSN solutions offered by Comcores.

Part 2: Opening the 5G Radio Interface

Carriers are now deploying 5G across the globe driven by the need to keep up with relentless mobile data growth. 5G New Radio (NR) operates at higher frequencies to increase bandwidth, but at the expense of range. There will therefore be a need for a much larger number of 5G RUs to provide the same coverage. The availability of cost-effective, reliable and open 5G radio units is therefore critical.

Accelerating 5G virtual RAN deployment

This whitepaper provides an overview of the O-RAN Alliance and the value provided by O-RAN to the carrier industry along with a brief introduction to Comcores, our O-RAN solutions and our role in the O-RAN eco-system.

Frequently asked questions about CPRI IP cores

What is CPRI Synthesizable Transactor?

CPRI Synthesizable Transactor is a CPRI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this CPRI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPRI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP