Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
- Control Logic
- Available
- March 2015
Control Logic Accelerator IP cores accelerate state-machine-heavy and control-oriented processing tasks in modern SoC and ASIC designs.
These IP cores help offload control-path work, scheduling, sequencing, and real-time coordination from general-purpose processors in complex datapaths
This catalog allows you to compare Control Logic Accelerator IP cores from leading vendors based on latency, determinism, integration flexibility, and process node compatibility.
Whether you are designing embedded control systems, communications pipelines, industrial automation, or accelerator orchestration, you can find the right Control Logic Accelerator IP for your application.
Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with width expansion
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with protocol for multiway pipeline fork and join capability
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
HIgh-speed & Low latency Search Engine
tCAM-IP is a high performance, extremely low latency and configurable ternary content-addressable memory IP.
Extremely Low Latency Matching Engine Synthesizable IP Core
Axonerve is a next generation variant of the content-addressable memory (CAM) solution.
Behavioral knowledge space combination rule core with parallel operation
So_ip_ecr_bks_p core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Behavioral knowledge space combination rule core with serial operation
So_ip_ecr_bks_s core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Weighted majority voting combination rule core with parallel operation
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classificat…
Majority voting combination rule core with parallel operation
So_ip_ecr_mv_p core can be used to implement several Majority Voting combination rules to calculate the ensemble classification o…
Majority voting combination rule core with serial operation
So_ip_ecr_mv_s core can be used to implement the several variants of the Majority Voting combination rule to calculate the ensemb…
CRC (Cyclic Redundancy Check) Calculation Unit
CRC (Cyclic Redundancy Check) calculation unit using a polynomial generator from 8-bit/16-bit/32-bit data words CRC code.
A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued repre…
100G UDP Offload Engine - Offloads UDP packet processing for efficient, high-speed networking
The 100G UDP Offload Engine in Verification IP (VIP) offloads UDP packet processing to specialized hardware, enhancing data trans…
100G TCP/IP Offload Engine - Validates high-speed network traffic, optimizing flow and reliability
The 100G TCP/IP Offload Engine is a cutting-edge Verification IP designed to streamline the testing of high-speed networking inte…
Maintains a database of outstanding orders.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.