Vendor: Curious Corp. Category: MIPI

Camera Combo Receiver - 1.5Gbps - 4-Lane - TSMC 40LP

The CL12662K4R1AM2JIP1500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) a…

Contact Provider Request Datasheet
TSMC 40nm LP Silicon Proven View all specifications

Overview

The CL12662K4R1AM2JIP1500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12662K4R1AM2JIP1500 is designed to support data rate in excess of maximum 1.5Gbps utilizing sub-LVDS / MIPI D-PHY v1-1 interface specification. The CL12662K4R1AM2JIP1500 can change Interface type to same PAD for changing mode.

Key features

  • MIPI D-PHY v1-1 / MIPI CSI2 compliant
  • Supporting for four kind Differential Input Signals:
    • 1) sub-LVDS (Maximum 1.0Gbps)
    • 2) MIPI D-PHY (Maximum 1.5Gbps)
  • Maximum Input Clock Frequency: ~750MHz
  • Maximum Input Data Transfer Rate: ~1.5Gbps
  • Maximum Output Clock Frequency: ~187.5MHz
  • Power Supply: Vcc=1.8V (IO and Analog) Vdd=1.1 V (Inside Core)
  • Maximum Lane Number: 4-Lane
  • Parallel Outputs: 8/10/12/14/16bit support
  • Including Power Down Mode
  • TSMC 40LP Process
  • Various process porting support available ( Please contact us. )
  • Supporting Link-layer: CD12662IP soft macro

Benefits

  • This IP is supported almost CMOS Image Sensor. Thus if when the customer want to use customer's LSI other system set, the customer don't need to change IP, because this IP can change Interface type to same PAD for changing mode pin.
  • The system customer can select from many CMOS image sensor for using out IP.
  • We are updating CMOS Image Sensor's modelnumber of verify operation for getting information from customer and ourself at all time.
  • If the customer need combo Link-layer, we can provide them and can support system.
  • We are provided CIS and TX Verilog Model. Thus the customer can confirm function by verilog simulation status.

Applications

  • Camera Application
    • Security Camera
    • Mobile-Phone Camera
    • DSC(Digital Still Camera)
    • Medical Camera
    • SLR
    • 3D Camera
    • Camcorder
  • ISP(Image Signal Processer)

What’s Included?

  • Verilog Model (verilog / vcs)
  • .db file / .lib(Option) file
  • symbol / LVS netlist / Hspice netlist(Option)
  • LEF, layer map file, layout technology file
  • Layout Verification Report (DRC & LVS), Command file
  • Datasheet (This file) /Application Note (Usage connection CIS)
  • Packaging and Layout Guideline / PCB Guideline
  • Static Delay Analysis (STA) Guideline
  • Testing Guideline (Option)
  • TX Verilog Model and Test Vector(Option)
  • CMOS Image Sensor Verilog Models(Option)

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 40nm LP Silicon Proven

Specifications

Identity

Part Number
CL12662K4R1AM2JIP1500
Vendor
Curious Corp.
Type
Silicon IP

Provider

Curious Corp.
HQ: Japan
CURIOUS Corporation was established in July, 2001. We develop Analog/Mixed Signal (Analog/Digital Mixture) IP and IC ( Integrated Circuits). Especially,we are good at interface circuits and imaging capture circuits. And our IP and IC are used mobile-phone and flat panel display. In the future, all information processing machines will be presumed to be connected over a form of network or another. As such demands for these machines are expected to increase considerably in the ever-expanding world of communication with this increase demands for the LCD Driver will also undoubtedly rise. With the present lack of analog design capacity in the world due to a shortage of analog engineers. Our main purpose is to work hard to provide our customers with the best expert advice and services possible.
Contact Curious Corp.

Learn more about MIPI IP core

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.

MIPI: Powering the Future of Connected Devices

From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.

Frequently asked questions about MIPI IP cores

What is Camera Combo Receiver - 1.5Gbps - 4-Lane - TSMC 40LP?

Camera Combo Receiver - 1.5Gbps - 4-Lane - TSMC 40LP is a MIPI IP core from Curious Corp. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP