BitBLT Graphics Hardware Accelerator (Avalon Bus)

The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).

The DB9100AVLN also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps. A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.

The DB9100AVLN also contains a programmable Alpha Blend unit, blending two bitmaps into one.

The DB9100AVLN interfaces to a microprocessor and frame buffer memory via the Altera Avalon Interconnect, providing a lower power solution. The DB9100AVLN contains a DMA Command Linked-List Processing Unit, for independently reading and processing graphics commands from the host processor.

• Bit Block Transfer – 3 Independent Memory Sources of data:
  • On-Screen & Off-Screen Data Block (SRC)
  • Off-Screen Fixed Pattern Data Block (PTN)
  • On-Screen visible Data Block (DST)
• Raster Operations (ROP) performed on Block Transfers:
  • 256 Raster Operations
  • ROP0, ROP1, ROP2, & ROP3 operations
  • Includes industries most popular 16 ROPs
• BitBLT Draw Features:
  • Pixels, Horizontal & Vertical Lines
  • Overlapping & Non-Overlapping Block Transfers
  • Solid Color Block Fills
  • FONT Monochrome Bitmap to Color Expansion, either Transparent or Opaque
  • Rotation Block Transfers: 0, 90, 180, 270 degrees
  • Block Stretch on X & Y Axis
  • Alpha Blending
  • Sprite Moves
• Command FIFO or Link-List Display Processing Unit:
  • Simplifies Processor Interface
  • Minimizes Processor Overhead
• Frame Buffer & Display Features Supported:
  • Display Resolutions 4K x 4K
  • 4 GB Memory Range
  • 8, 16 , 24, & 32 bits-per-pixel color depths
• Interrupt Controller with 3 sources of internal interrupts with masking control
• Reference Software Driver Included
  • Reference Driver
  • Graphics API Reference Design
• On-Chip Interconnect Compliance - Avalon:
  • Avalon Interface Specification (MNL-AVABUSREF-2.0)
• FPGA Integration Support:
  • Altera Quartus II & Qsys Integration & ARM / NIOS II EDS Reference Design
  • Xilinx Vivado IP Integrator & Reference Design
• ASIC / ASSP Design-In Support:
  • Compliance to RTL Design, Coding, & Verification Standards
  • Digital Blocks Support Services
• Compatible with Digital Blocks DB9000 Family of TFT LCD Controller IP Cores and Reference Designs
• Fully-synchronous, synthesizable Verilog RTL core.

• The DB9100AVLN is available in RTL Verilog, along with synthesis scripts, a simulation test bench with expected results, reference design, datasheet, and user manual.