Vendor: Curious Corp. Category: Video Transport

Sensor/Display MIPI A-PHY Sink IP

The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking ap…

TSMC 40nm LP eFlash View all specifications

Overview

The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS and autonomous drive subsystems. It supports applications that require long reach (up to 15 meters), error-free links, and high EMI immunity requirement.

PHY IP supports the SINK function of MIPI A-PHY Gear-2 stated in standard specification. It supports data rate up to 4Gbps with integrated mixed signal circuit, high performance RX equalizer, fast tracking Clock and Data Recovery, on chip optional termination resistor calibration.

Key features

  • Compliant with MIPI A-PHY specification version 1.0
  • Support Gear-2 up to 4Gbps
  • Support data bus width: 20-bit parallel interface
  • Support 2 lanes
  • Support Uplink Driver @ 100Mbps
  • Selectable input clock frequency: 25MHz
  • Maximum output clock frequency at 200MHz
  • Supports Single-ended coaxial or shielded twisted-pair (STP) cable up to 15m
  • Support A-PHY PMD layer by HARD macro
  • Support AEC-Q100 (Grade 1) for automotive applications
  • High performance Data and clock recovery.
  • Analog monitor port for test and debug
  • Embedded termination Resistor and optional calibration function
  • Supporting Link IP CD12912IP200 (PHY layer PCS, RTS and Data Link) soft macro
  • Native Protocol Adaption layer supports (Option)

Block Diagram

Benefits

  • CL12911 and CL12912 support MIPI A-PHY interface.
  • A-PHY is long-reach, serializer-deserializer (SerDes) physical layer interface for automotive applications such as advanced driver assistance systems, autonomous driving systems and other surround-sensor applications, including cameras and in-vehicle infotainment displays. A-PHY forms a family of specifications designed to provide end-to-end connectivity with safety and security built-in.
  • With a reach of up to 15 meters, MIPI A-PHY offers high-speed performance with an ultra-low packet error rate for unprecedented reliability, ultra-high immunity to electromagnetic interference effects.

Applications

  • Automotive Application
  • Advanced driver assistance systems
  • Autonomous driving systems
  • Surround-sensor applications
  • Camera
  • Display

What’s Included?

  • GDSII
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behavior model
  • Netlist & Timing information
  • Datasheet, Packaging and Layout Guideline / PCB Guideline
  • LVS/DRC verification reports
  • Static Delay Analysis (STA) Guideline
  • Testing Guideline (Option)Testing Guideline (Option)

Silicon Options

Foundry Node Process Maturity
TSMC 40nm LP eFlash

Specifications

Identity

Part Number
CL12912IP4000
Vendor
Curious Corp.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Curious Corp.
HQ: Japan
CURIOUS Corporation was established in July, 2001. We develop Analog/Mixed Signal (Analog/Digital Mixture) IP and IC ( Integrated Circuits). Especially,we are good at interface circuits and imaging capture circuits. And our IP and IC are used mobile-phone and flat panel display. In the future, all information processing machines will be presumed to be connected over a form of network or another. As such demands for these machines are expected to increase considerably in the ever-expanding world of communication with this increase demands for the LCD Driver will also undoubtedly rise. With the present lack of analog design capacity in the world due to a shortage of analog engineers. Our main purpose is to work hard to provide our customers with the best expert advice and services possible.

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is Sensor/Display MIPI A-PHY Sink IP?

Sensor/Display MIPI A-PHY Sink IP is a Video Transport IP core from Curious Corp. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP