Vendor: MVD Cores Category: Video Transport

DVB Remultiplexer N-to-M

The MVD Remultiplexer core analyses the MPEG TS stream inputs and gives access to the followings information and statistics : * I…

Contact Provider Request Datasheet

Overview

The MVD Remultiplexer core analyses the MPEG TS stream inputs and gives access to the followings information and statistics :

* Incoming TS Stream features (TS_ID, NetworkID, Original_NetworkID, Version, Tables, ...)
* Incoming/ Payload/ Outcoming rates
* Program List and bandwidth for each program.
* Program Information (Names)

Then, it filters user selected programs and regenerates PSI/SI tables such as PAT, SDT, NIT (according to programmed mode), PMTs, EITs (according to configuration).

TOT, TDT, not filtered PMT programs and others PID which do not correspond to any program or PSI/SI tables are passed through.

EIT and PMTs are re-generated according to the modifications to apply to the output stream.

BAT and RST are filtered. CAT and related PIDs (EMM) are filtered according to the configuration of the remultiplexer.

Possibility to adapt output TS to customer needs by changing TS_ID, Network_ID, OriginalNetworkID, Service_ID , Services Names etc...

The DVB Remultiplexer core allows the filtering of programs of DVB MPEG TS flows compliant with the standards :

* UIT-T H222 (02/00) / ISO13818-1
* ETSI EN 300 468 v1.8.1 (2008-7)

Key features

  • Drop-in module for Spartan 6, Virtex-6, Artix-7, Kintex-7, Zynq FPGAs
  • N SPI input / M SPI output (N and M from 1 to 8)
  • Adapt one or several MPTS/SPTS stream into one or several MPTS by filtering and multiplexing complete services
  • SFN MIP table insertion independent for each output (for DVB-T core control)
  • Management of PSI/SI tables (automatic tables generator) according to ETS300468 and ISO 13818-1.
  • Configurable via an RS232 link or I²C link
  • Service filtering and insertion of custom NIT
  • Full PCR re-stamping
  • Master/Slave control of input/output mux flows
  • Statistical service bandwidth estimation per input
  • Maximize output payload bandwidth thanks to smoothing FIFO.
  • Smoothing FIFO can be implemented as block RAM or external Synchronous SRAM memory
  • Size of the output smoothing FIFO is configurable.
  • Full synthesizable RTL design (not delivered) for easy customization
  • Netlist version available for ISE 12 and later versions
  • CPU Interface to control MVD Modulator CORE

Block Diagram

MVD_DVB_REMUXN-M block diagram

Applications

  • The MVD DVB Remultiplexer allows to adapt and multiplex transmodulator bandwidth from several sources as DVB-S towards one or several modulator as DVB-T, IP-TV or J83 A/B/C.

What’s Included?

  • Datasheet
  • Netlist for core generation
  • VHDL top file
  • VHDL source code : can be delivered as an option under NDA and other specific clauses

Specifications

Identity

Part Number
MVD_DVB_REMUXN-M
Vendor
MVD Cores
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

MVD Cores
HQ: France
MVD Cores is an engineering team highly specialized in Digital Video Broadcasting (DVB) and FPGA technologies. We provide IP cores for Processing, Transporting and Transmission of MPEG, DVB, ATSC & IPTV standards for Xilinx FPGAs. The products and services catalog contains a wide range of on-the-shelf IPs to build solutions to carry MPEG-TS to RF. Our IPs cover almost all worldwide standards of current technologies for broadcasting over Digital Terrestrial Television (DTT), Cable TV (CATV) and Satellite.
Contact MVD Cores

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is DVB Remultiplexer N-to-M?

DVB Remultiplexer N-to-M is a Video Transport IP core from MVD Cores listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP