ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications

The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA). The DSP-enhanced ARC processor families support a broad portfolio of certified audio codecs and post-processing software from a range of popular standards including Dolby, DTS, Microsoft and SRS.

With patented configuration technology, the cores can be easily customized to meet any application requirement from ultra-small task-specific controllers robust application processors. Additionally, the extendible instruction set makes it possible for customers to add instructions and operations to provide additional acceleration and more efficient operation, resulting in highly differentiated designs that cannot be built with standard, off-the-shelf DSPs or CPUs.

These processors are also designed to be tolerant to high memory latencies. Compared to other solutions in the market, the impact of latency on the processor load is negligible, making the ARC processors the best solution for systems like video and graphics IP, where DDR memory is shared with other resources.

DSP-Enhanced ARC EMxD Processors for Audio

The ARC EMxD family, which includes the ARC EM5D processor, ARC EM7D processor, ARC EM9D processor, and EM11D processor, are specifically designed for ultra low-power embedded DSP applications. These processors are based on the enhanced ARCv2DSP ISA, which adds over 150 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The processors feature a power-efficient unified 32x32 MUL/MAC unit, support for fixed point DSP vector and single instruction multiple data (SIMD) operations. The ARC EM DSP family features a balanced 3-stage Harvard architecture pipeline that provides efficient throughput and the cores offer excellent real-time control and DSP performance.

ARC DSP-Enhanced HS4xD Processors for Audio

The HS45D and HS47D processors support more than 150 DSP-optimized instructions, delivering a unique combination of high-performance control and high-efficiency digital signal processing. To speed the execution of math functions, the HS4xD cores give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a optional IEEE 754-compliant floating point unit (single- or double-precision or both). The ARC HS4xD processors are compatible with the ultra-low power ARC EMxD processors and have the same instruction set, making it easy to migrate code between the two processor families.

• Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
• Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
• RAM configuration optimized for efficient area and power
• Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
• Synopsys ARC XY Advanced DSP solution delivers the performance of dedicated DSP cores
• Synopsys ARCompact 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets
• Delivered as synthesizable RTL source code (Verilog®) to be fully compatible with industry-standard design methodologies and tool flows
• XY Advanced DSP solution delivers the performance of dedicated DSP cores
• Synopsys ARC MetaWare Development Toolkit, xCAM and nSIM simulators