Vendor: eSi-RISC Category: I2C / I3C

APB I2C master and slave

The eSi-I2C core implements the I2C two-wire protocol.

Overview

The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB slave interface and so can be driven by software or via DMA.

Key features

  • Multi-master / slave operation.
  • Clock stretching.
  • 7 and 10-bit addresses.
  • Programmable bit rate.
  • Programmable digital filtering for SDA and SDL inputs.
  • Configurable TX and RX FIFOs.
  • AMBA 3 APB slave interface.
  • DMA flow-control interface.

Block Diagram

What’s Included?

  • Verilog RTL
  • Testbench
  • Simulation and synthesis scripts
  • Documentation
  • C API

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
eSi-I2C
Vendor
eSi-RISC
Type
Silicon IP

Provider

eSi-RISC
HQ: UK
eSi-RISC designs and licenses the eSi-RISC range of configurable, low-power, RISC CPU IP cores, as well as associated peripheral IP cores and software development tools. The eSi-RISC processors are unique in being configurable from a base 16-bit core (eSi-1600) to a 32-bit, multi-core CPU with optional caches (eSi-3250), to a high-performance DSP core with 64-bit fixed-point SIMD and floating point support (eSi-3264). As well as supplying individual cores, eSi-RISC can develop complete SoC sub-systems combining CPUs, memory and peripherals (DMA, memory-controllers, I2C, UART, SPI, etc.), using an AMBA AXI/AHB/APB based interconnect, generated automatically using our eSi-SoC EDA tool.

Learn more about I2C / I3C IP core

From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems

The I2C (Inter-Integrated Circuit) Bus invented in 1980 by Philips Semiconductors (NXP Semiconductors today) was a massive step forward in simplifying communications in embedded systems. It is a simple two-wire interface for synchronous, multi-master/multi-slave, single ended serial communication. Fast forward 45 years to today and it is still widely used for attaching low speed peripheral Integrated Circuits (ICs), processors and microcontrollers. But silicon today has changed...

Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future

Early in my career selling chips for Motorola Semiconductor, the ability to spin derivative microcontroller chips for a customer’s specific requirement was relatively straightforward. If the volume looked reasonable, we would tape-out a new chip with a few added features because mask costs and wafers were relatively inexpensive at the larger process nodes. The customer won by getting an MCU tailored to their specific need, and Motorola won by gaining a more committed customer plus another SKU that could be sold to other customers – boosting ROI. With the migration to higher cost FinFET nodes, those times are long gone as the economics no longer work.

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

Frequently asked questions about I2C / I3C IP cores

What is APB I2C master and slave?

APB I2C master and slave is a I2C / I3C IP core from eSi-RISC listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP