Vendor: SmartDV Technologies Category: Coherency

AMBA ACE5-Lite Synthesizable Transactor

AMBA ACE5-Lite Synthesizable Transactor provides a smart way to verify the ARM AMBA ACE5-Lite component of a SOC or a ASIC in Emu…

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Overview

AMBA ACE5-Lite Synthesizable Transactor provides a smart way to verify the ARM AMBA ACE5-Lite component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA ACE5-Lite Synthesizable Transactor is fully compliant with standard AMBA ACE5-Lite Specification and provides the following features

Key features

  • Compliant with the latest ARM AMBA ACE5-Lite Protocol Specification.
  • Supports ACE5-Lite Master and Slave.
  • Supports all ACE5-Lite data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address, data and response phases. Separate read and write channels.
  • Support for burst-based transactions with only start address issued.
  • Slave and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Ability to issue multiple outstanding transactions.
  • Out of order transaction completion support.
  • Protected accesses with normal/privileged, secure/non-secure and data/instruction.
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction
  • Atomic access support with normal access and exclusive access
  • Longer bursts up to 256 beats.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Ability to break longer bursts into multiple shorter bursts
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • ACE-Lite specific features
    • Supports functionality to verify ACE-Lite.
    • Supports all ACE-Lite transaction types.
    • Support for multiple outstanding ACE-Lite transactions.
    • Supports all write/read responses.
    • Fine grain control of Initiating Master transaction including main memory access
    • Fine grain control of Interconnect generated main memory access transactions.
    • Shareable and Non-shareable transactions.
    • Broadcast cache maintenance operations.
  • ACE5-Lite specific features
    • Atomic Transactions
    • Cache Stash Transactions
    • Deallocating Transactions
    • CMO for Persistence
    • Data Check
    • Poison
    • QoS Accept
    • Trace signals
    • User Loopback
    • Wakeup signals
    • Untranslated Transactions
    • Non-secure Access Identifiers
  • ACE5Lite-DVM specific features
    • Atomic Transactions
    • DVM v8.1
    • Cache Stash Transactions
    • Deallocating Transactions
    • CMO for Persistence
    • Data checking
    • Poison
    • QoS Accept
    • Trace signals
    • User Loopback
    • Wakeup signals
    • Coherency connection signals
    • Untranslated Transactions
    • Non-secure Access Identifiers
  • ACE5-LiteACP specific features
    • Data width and burst size upto 128 bits
    • Burst length 1 or 4 beats
    • Cache Stash Transactions
    • Wakeup signals
    • Data Check
    • Poison
    • Trace signals
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control ACE5-Lite functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events on bus.

Block Diagram

AMBA ACE5-Lite Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA ACE5-Lite Synthesizable testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
AMBA ACE5-Lite Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about Coherency Interconnect IP cores

What is AMBA ACE5-Lite Synthesizable Transactor?

AMBA ACE5-Lite Synthesizable Transactor is a Coherency IP core from SmartDV Technologies listed on Semi IP Hub.

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Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

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