2D Graphics Hardware Accelerator (AXI Bus)

The Digital Blocks DB9200AXI 2D Graphics Hardware Accelerator / Engine Verilog IP Core renders graphics frames as follows:

• Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
• Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
• Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
• Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit

The DB9200 2D Graphics Hardware Engine provides options for higher graphics performance as a Graphics Processing Unit (GPU) as follows:

• Display List Processing Unit - reads in the graphics instructions for execution
• Parallel Pixel Processing - as wide as the AXI Interconnect Data
• Memory Interface Units - with DMA Controller that can burst in and out pixels, helping to unlock the graphics memory bottleneck.

• Bit Block Transfer – 3 Independent Memory Sources of data:
  • On-Screen & Off-Screen Data Block (SRC)
  • Off-Screen Fixed Pattern Data Block (PTN)
  • On-Screen visible Data Block (DST)
• Raster Operations (ROP) performed on Block Transfers:
  • 256 Raster Operations
  • ROP0, ROP1, ROP2, & ROP3 operations
  • Includes industries most popular 16 ROPs
• BitBLT Draw Features:
  • Pixels, Horizontal & Vertical Lines
  • Overlapping & Non-Overlapping Block Transfers
  • Solid Color Block Fills
  • FONT Monochrome Bitmap to Color Expansion, either Transparent or Opaque
  • Rotation Block Transfers: 0, 90, 180, 270 degrees
  • Block Stretch on X & Y Axis
  • Alpha Blending
  • Sprite Moves
• Line Draw Graphics Operations:
  • Pixel Draw
  • Line (Vector) Draw
  • Poly Line Draw (up to 16 segments)
  • Circle Draw
  • Ellipse - (Option – Please contact Digital Blocks)
• Command FIFO or Link-List Display Processing Unit:
  • Simplifies Processor Interface
  • Minimizes Processor Overhead
• High-performance Read/Write DMA Controllers for data transfer from/to memory
• Frame Buffer & Display Features Supported:
  • Display Resolutions 4K x 4K
  • 4 GB Memory Range
  • 8, 16 , 24, & 32 bits-per-pixel color depths
• Interrupt Controller with 3 sources of internal interrupts with masking control
• Reference Software Driver Included
  • Reference Driver
  • Graphics API Reference Design
• On-Chip Interconnect Compliance - AXI:
  • AMBA AXI Protocol Specification (V2.0)
• FPGA Integration Support:
  • Altera Quartus II & Qsys Integration & ARM / NIOS II EDS Reference Design
  • Xilinx Vivado IP Integrator & Reference Design
• ASIC / ASSP Design-In Support:
  • Compliance to RTL Design, Coding, & Verification Standards
  • Digital Blocks Support Services
• Compatible with optional Digital Blocks DB9000 Family of TFT LCD Controller IP Cores and Reference Designs
• Fully-synchronous, synthesizable Verilog RTL core.

• The DB9200AXI is available in RTL Verilog, along with synthesis scripts, a simulation test bench with expected results, reference design, datasheet, and user manual.