2/64/128 CMOS/ECL PLL high-frequency divider
The CMOS high-frequency divider consists of two independent circuits.
Overview
The CMOS high-frequency divider consists of two independent circuits. The first divider is a set of serially connected CMOS dividers with a dividing ratio 2. The second circuit is based on ECL logic and has differential signal. The reference current source of ECL circuit has temperature dependent and temperature independent modes. The buffer-commutators are used to output the signal of a frequency divided by 2, 64 or 128.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
Key features
- TSMC BiCMOS SiGe 180 nm
- Fixed dividing ratio 128 with complementary outputs of dividers on 2 and 64
- Two divider types: CMOS and ECL
- Temperature dependent mode of reference current
- Portable to other technologies (upon request)
Block Diagram
Applications
- PLL frequency synthesizer
What’s Included?
- Schematic or NetList
- Layout or blackbox
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
Specifications
Identity
Provider
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Frequently asked questions about PLL IP cores
What is 2/64/128 CMOS/ECL PLL high-frequency divider?
2/64/128 CMOS/ECL PLL high-frequency divider is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.