10M End Station Controller

Silicon Agnostic, Silicon proven and Comprehensive hardware and software solution

The 10M End Station Controller IP is a comprehensive hardware and software solution. It contains a Media Access Controller (MAC), a Time Of Day (TOD) system and an optional MACsec protection block. The solution can interface with nearly any microcontroller or embedded processor system, either via SPI or AXI Memory Mapped host interface. The host interface can simultaneously transfer both transmit and receive packets, and the End Station Controller supports store and forward or cut-through packet handling.

The 10M End Station Controller IP supports 10M half- and full-duplex operation and utilize a standard MII/RMII interface to communicate with 10BASE-T1S, 10BASE-T1L and 10BASE-T Ethernet physical layer devices. It includes an MDIO controller for configuration and management of the Ethernet physical layer device.

The optional MACsec protection block provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE. It is configurable to have multiple Security Entities, SecYs to support multiple Connectivity Associations per port for traffic differentiation.

The 10M End Station Controller IP supports Timing and Synchronization for Time‐Sensitive Applications according to IEEE 802.3AS including the IEEE 802.1ASds amendment required for half-duplex operation. The timestamp for packets can be based on end of the Start of Frame Delimitator (SFD) on the MII/RMII interface or via more accurate packet indications from the Ethernet physical layer device if available. The TOD system includes the internal wall clock and phase adjuster for the wall clock to minimize software processing overhead.

The 10M End Station controller IP include a comprehensive software package with device drivers for several operating systems, a software stack for 802.1AS and a complete demonstration system based on FreeRTOS.

The solution is available as technology independent RTL source code (System Verilog) or encrypted netlist for ASIC and FPGA implementations. Furthermore, FPGA based hardware platforms are available for evaluation and prototyping.

The 10M End Station Controller IP is available in two versions depending on the host interface type.

Versatile Solution

• 1 x 10M 10BASE-T1S Ethernet Port
• OPEN Alliance 10BASE‑T1x MAC‑PHY SPI or AXI-MM host interface
• 802.1AS Time Synchronization
• Wall clock, Phase adjustment & Packet timestamping
• Integrated Media Access Controller (MAC)
• Optional MACsec frame protection
• FreeRTOS Software Development Kit
• 1AS software stack
• Functional Safety Manual, FMEDA

Silicon Agnostic

• Designed in Verilog and targeting both ASICs and FPGAs

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• IP in SystemVerilog, Source code or Encrypted RTL
• Comprehensive documentation, including User Manual, Release Note and Product Brief
• Simulation Environment, including basic test environment, test cases and test scripts
• Software demo application, Complete Linux system with
  • Full integration into Linux
  •  Netconf for configuration & management
• Software drivers, C code, Linux device driver, FreeRTOS driver
• IEEE 802.1AS software stack, C code
• Demo: Complete example design targeted AMD/Xilinx ZCU102 hardware platform, with other hardware platforms on request
• Access to support system and direct support from Comcores Engineers
• Timing Constraints in Synopsys SDC format (optional)
• Synopsys Lint (optional)
• Synopsys Lint waiver (optional)