Uniquify Releases Industry's First Smart DDR Memory Controllers

-- Uniquify, Inc., the leading edge IP solutions provider, released the industry's first smart high performance DDR Memory Controllers with Self-Configuring Logic (SCL) technology to solve system level timing issues.

"This is for any company that would need an interface to external high performance DRAM's but does not want to have to concern themselves with design integration difficulties and physical implementation challenges of high performance DDR," says Mahesh Gopalan, Director of Engineering at Uniquify. "We at Uniquify developed a unique solution to solve system level timing issues such as package/board/DDR-memory timing uncertainties."

This is for any company that would need an interface to external high performance DRAM's but does not want to have to concern themselves with design integration difficulties and physical implementation challenges of high performance DDR
Most DDR controllers do not address how to solve these tough system level timing issues. There's difficulty capturing accurate delay numbers for package or board traces before the system is built. Furthermore, most DDR controllers have to be designed for multiple DDR SDRAM modules from various vendors that have different timing specifications.

Uniquify's patent-pending SCL solution addresses these issues by allowing a wider range of capturing timing window in read operation to account for system level timing uncertainties. This unique feature of the DDR2 and mobile DDR controller virtually eliminates any risk in high performance DDR designs and ensures first time working silicon.

Uniquify's DDR2 and mobile DDR memory controller IP are complete DDR SDRAM solutions incorporating a compact, highly configurable memory controller and PHY macro compiler to resolve tough timing problems such as data/clock skew, setup/hold time, and complex physical implementation issues.

Product highlights include:

• Patent-pending Self Configuring Logic (SCL) technology virtually eliminates system level timing issues
• Complete DDR SDRAM solution including memory controller and physical interface module (PHY) compiler.
• Low read data capture latency achieved by a unique flop-based logic
• Fast turn-around time between read and write operations
• Support for 1 to 8 chip-select signals and 4 or 8 banks on each chip select
• 24 command deep pipeline hides access latency
• Fully configurable ODT window

Uniquify is a leading edge IP solutions provider. The company has a proven track record of successful tape outs and joint SoC development projects in 65nm, 90nm, and 130nm technologies. Uniquify's completely U.S. based team provides logical and physical integration support. Uniquify specializes in low power, high performance and fully configurable DDR designs.