NurLogic announces Silicon Validation of its Quad 3.125 gbps SerDes Transceiver IP Cores

NurLogic delivers another homerun with its silicon-proven 0.13-micron SerDes IP cores

SAN DIEGO – December 9, 2002 – NurLogic Design, Inc. a developer of high bandwidth connectivity solutions, today announced another first-time silicon success with the release of its silicon-proven portfolio of SapphireLink™ serializer/deserializer (SerDes) transceiver Intellectual Property (IP) cores in 0.13-micron technology. 

Providing customers with silicon-proven SerDes IP cores fills an essential need in the marketplace by accelerating customer’s time to market.  “Our customers don’t have time or money to waste re-spinning their designs when other companies’ IP fails in silicon,” said Lisa Lipscomb, vice president of marketing for NurLogic.  “At NurLogic, we have consistently provided our customers with first-time silicon IP success, ensuring product reliability by focusing on complex integration issues and bringing our analog/mixed signal expertise to bear.”  NurLogic’s SerDes product line has been integrated into leading server workstation designs with remarkable success.

The outstanding results of the characterization tests reflect the design expertise of NurLogic’s team.  “Our first silicon performance exceeds XAUI and InfiniBand specifications on both sides of the link, with an output jitter performance of 0.25 UI at 3.125 Gbps,” said Benny Malek Khosravi, vice president of engineering for NurLogic.  “Furthermore, performance of our CDR block and serial link inputs surpass specifications and we have demonstrated recovery of clock and data based on an eye opening of 0.30 UI at 3.125 Gbps.”

“Our team has once again hit a home run and our customers are very happy with the performance.  With our high level of integration, channel scalability, power and area scalability, and our demonstrated performance, we provide our customers with viable solutions for a variety of applications now and as their next-generation products evolve.”

NurLogic has developed the industry’s smallest, low-power, highest performance SerDes available on the market.  NurLogic’s SapphireLink™ serializer/deserializer (SerDes) IP cores in 0.13-micron technology operate from 1 to 4 Gbps and consume less than 80mW/channel of power.  NurLogic is currently developing its next-generation SerDes portfolio.

PRODUCT HIGHLIGHTS
NurLogic’s SapphireLink SerDes cores are implemented as 4-channel (Quad) physical representations that allow for ease of integration. This modular design allows for multiple instantiations without performance degradation. The SerDes IP cores’ well-defined architecture provides a comprehensive feature set that allows System-on-a-Chip (SoC) designers extensive flexibility for a wide range of system interface options and system level applications including 10-Gigabit Ethernet (XAUI Interface), InfiniBand, Gigabit Ethernet, and Fiber Channel.

FEATURES:

• 3.125 Gbps per channel, 12.5 Gbps for quad core
•  Low Power Dissipation – 80mW per TX/RX pair
•  8B/10B Encode/Decode with bypass option and comma detect
•  Clock and Data Recovery (CDR) on each RX channel
•  Loss of Signal (LOS) detect, up to 90 bits
• Built-In-Self-Test (BIST) and Pseudo Random Bit Sequence (PRBS) with multiple  pattern options including K28.5/K28.7/D16.2
•  Hot swap capable I/Os

FLEXIBILITY:

• Superior noise isolation allows high level of integration
•  Double or single data rate option
•  Wirebond or flip-chip options

AVAILABILITY
NurLogic offers the SapphireLink SerDes core portfolio as “hard” IP blocks that include support for leading EDA tools and foundry technologies.  NurLogic's 0.13-micron SerDes cores are currently available to license.  Leaders in analog and digital design, NurLogic provides expert integration support to help customers more easily integrate the SapphireLink SerDes cores into their designs. Eye Diagrams, customer demonstrations and pricing are available upon request.

About NurLogic Design, Inc
NurLogic Design, Inc. provides high-bandwidth connectivity solutions to the networking and communications industries. NurLogic utilizes its expertise in analog/mixed-signal design and high-performance I/O bus interfaces to develop silicon-proven Intellectual Property (IP) to deliver value-add to its customers. NurLogic products are targeted at CMOS and silicon germanium technologies, and include high-speed connectivity IP, analog and mixed-signal IP, and foundation IP. Based in San Diego, California, NurLogic has regional sales offices in Massachusetts and Silicon Valley. NurLogic is a privately held corporation.

Headquarters: 5580 Morehouse Drive, San Diego, Calif. 92121
Tel: 1-877-NURLOGIC. On the web at www.nurlogic.com.

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NurLogic is a trademark of NurLogic Design, Inc.