Avery Design Systems Announces eMMC 5.0 Verification IP Solution
ANDOVER, MA. -- August 12, 2013 – Avery Design Systems Inc., a leader in verification IP (VIP), today announced availability of its eMMC 5.0 verification solution.
eMMC-Xactor are complete verification solutions enabling design and verification engineers to quickly and extensively test the functionality of memory systems. The VIP includes:
- Host and Device models
- Compliance testsuite
- Comprehensive protocol checks
- Multi-level protocol analyzer trackers
- Functional coverage model
Models and compliance testsuites are developed in native SystemVerilog and supports UVM verification environments.
“Avery is focused on delivering industry leading VIP for the rapidly emerging SSD and other storage-related standards built on top of PCIe, USB, and MIPI base protocols”, says Chilai Huang, president of Avery Design Systems. “Our solution enables designers to thoroughly verify their designs functionally adhere to the new SCSI Express standard and effectively pinpoint areas of non-compliance or performance bottlenecks.”
Visit us at the Flash Memory Summit held on August 13-15 in booth #826.
Avery supports a full range of embedded storage and SSD VIPs including eMMC, SD/SDIO, Universal Flash Storage (UFS), SCSI Express (SOP/PQI), NVM Express, SATA Express, SATA, USB Attached SCSI (UASP), and ONFI/Toggle Flash.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, UAS/BOT, AMBA, UFS, MIPI UniPro/M-PHY, DDR/LPDDR, NVM Express, SCSI Express, SATA, SATA Express, eMMC, and SD/SDIO standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related News
- Arasan Announces eMMC 5.0 Total IP Solution at Mobile World Congress
- Arasan Chip Systems Announces the Industry's First SD 4.1 and eMMC 5.0 Combined Host Controller
- eInfochips announces eMMC 5.0 Verification IP
- SignatureIP Achieves PCI-SIG® PCIe® 5.0 Certification, Joining Elite Group on Official Integrators List
Latest News
- Virtusa Acquires Bengaluru based SmartSoC Solutions, Establishing Full-Stack Service Offering from Chip to Cloud and Driving Expansion into the Semiconductor Industry
- Consumer Electronics and AI Product Launches Lift 3Q25 Top-10 Foundry Revenue by 8.1%, Says TrendForce
- Joachim Kunkel Joins Quadric Board of Directors
- RaiderChip NPU leads edge LLM benchmarks against GPUs and CPUs in academic research paper
- SEMIFIVE Secures AI Semiconductor Design Projects in Japan, Accelerating Global Expansion with New Local Subsidiary