Altera to Feature High-Performance Memory Interface and PCI Express Solutions at Denali MemCon 2006
San Jose, Calif., September 11, 2006 -- Altera Corporation (NASDAQ:ALTR) will showcase its high-performance solutions for memory interfaces and PCI Express applications at Denali MemCon San Jose 2006. These demonstrations will show how Altera’s complete FPGA solutions enable designers to overcome design challenges, reduce design risk, maximize performance and accelerate time-to-market.
Visitors to Altera’s booth will see the following demonstrations:
- Stratix® II DDR2 SDRAM 667 Mbps
- PCI Express Development Board, Stratix II GX Edition
Technical experts from Altera will deliver presentations examining each of the following technologies:
- “Simplified Solutions for High-Speed Memory Interfaces Using Altera® FPGAs”
Wednesday, September 13, 2006
Track A: DRAM: Devices, Technologies and Roadmaps
Presenter: Sanjay Charagulla, System Architect
Time: 11:30 a.m.–Noon
- “Designing PCI Express-Based Systems Using FPGAs”
Thursday, September 14, 2006
Track B: PCI Express Technology
Presenter: Aashish Malhotra, IP and Technology Product Marketing Manager
Time: 1:30 p.m.–2:00 p.m.
September 12–14, 2006
Where:Denali MemCon San Jose
Altera Booth 414
Santa Clara Convention Center
5001 Great America Pkwy
Santa Clara, California 95054
Phone: (408) 748-0700
For more information or to register for Denali MemCon, visit www.denali.com/memcon/sanjose2006.html.
Related Semiconductor IP
- Xtal Oscillator on TSMC CLN7FF
- Wide Range Programmable Integer PLL on UMC L65LL
- Wide Range Programmable Integer PLL on UMC L130EHS
- Wide Range Programmable Integer PLL on TSMC CLN90G-GT-LP
- Wide Range Programmable Integer PLL on TSMC CLN80GC
Related News
- MemCon San Jose 2006 to Feature Windows Vista Symposium
- Rambus Announces Comprehensive PCI Express 5.0 Interface Solution
- NVM Express Delivers 1.2 Specification with New Data Center and Client Features for PCI Express Solid-State Drives
- Synopsys PCI Express IP Adds System-Level Data Protection Features for High-Performance Cloud Computing SoCs
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing