55nm Regulator IP Listing

3.3V to 0.75*VCC33A with 5mA driving capability with external capacitor; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process

• UMC
• 55nm
• LP

3.3V to 1.2V/0.9V with 100mA driving capability;Linear Regulator, UMC 55nm uLP/HVT Low-K Logic Process

• UMC
• 55nm
• ULP

3.3V to 1.2V/0.9V with 100mA driving capability;Linear Regulator, UMC 55nm uLP/RVT Low-K Logic Process

• UMC
• 55nm
• ULP

3.3V to 0.3V and VCCK-0.3V / 10mA voltage source for N/P well forward body bias, Linear Regulator, UMC 55nm uLP/RVT Low-K Logic P…

• UMC
• 55nm
• ULP

3.3v to 1.2v/150mA REG, Linear Regulator, UMC 55nm LP/RVT LowK Logic process

• UMC
• 55nm
• LP

3.3V to 1.2V with 150mA driving capability without external capacitor(Cap-less); use trimming ports (need e-Fuse IP); Linear Regu…

• UMC
• 55nm

3.3v to 1.0v/100mA REG, Linear Regulator, UMC 55nm SP/RVT LowK Logic Process

• UMC
• 55nm
• SP

3.3V to 1.2V with 180mA driving capability; Linear Regulator; UMC 55nm eFlash LowK Logic process

• UMC
• 55nm

3.3V input , Programmable Output 1.8V/1.2V with 300mA driving capability; Linear Regulator; UMC 55nm SP/RVT LowK Logic Process

• UMC
• 55nm
• SP

3.3v to 2.5v/5mA , REG, Linear Regulator, UMC 55nm LP/RVT Logic Process

• UMC
• 55nm
• LP

2.7V~3.3V to 1.8V with 150mA driving capability; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process

• UMC
• 55nm
• LP

The cell is a low power series 3.3V to 1.2V voltage regulator.

• UMC
• 55nm

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven