Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
Overview
Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
Key Features
- Decrease of fabrication costs
- Up to 50% denser than traditional register file compilers!
- Ultra low dynamic power
- Low power architecture even at nominal voltage: Up to 50% less consuming than standard memory compilers available at 90 nm LP
- Low voltage capability: 30% additional power consumption savings when operating at 1.0 V +/-10%
- Byte Write
- Flexible power routing: power ring or ring-less
- Low leakage
- Designed with the latest uLL PRBC from TSMC and a mix of HVT and SVT MOS (dominated by SVT to reach high speeds)
- Data retention mode to divide leakage by 5 compared to standard stand by mode
- Complete mismatch validation of the memory architecture taking in account local and global dispersion
- Architecture designed to enable robust low voltage operation
- Optional BIST for industrial fabrication test of instances
- Compliance with TSMC IP 9000 qualification process
Technical Specifications
Maturity
In_Production
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