High Speed Low Power JPEG Codec
Key Features
- Support Format
- Y:CB:CR= 4:2:2, 4:1:1
- Automatic Header Handling
- Generate/Read a variety of JPEG header information (Marker Code, Parameter) automatically.
- Quantization Table
- Incorporate 3 quantization tables for Y/Cb/Cr respectively as default.
- Possible to program tables from external CPU.
- Encode/Decode processing performance
- 92Mbyte/sec (@100MHz CLK)  Same performance for both ENC/DEC
Applications
- Any Kind of Graphic Applications
Deliverables
- Verilog RTL
- Synthesis Environment
- Test Environment
- Datasheet & Documents
Technical Specifications
Maturity
Production Proven
Availability
Now
Related IPs
- High Speed Low Power JPEG Codec IP Core
- High speed low latency AES-GCM pipeline, 100Gbps
- High performance, low power, 8-bit processor
- 400G/800G High Speed Ethernet Controller MAC/PCS/FEC
- 10G to 400G High Speed Channelized Ethernet Controller MAC/PCS/FEC
- 8-bit Baseline JPEG Codec with Optional Video Rate Control