UALink IP

UALink IP refers to semiconductor intellectual property (IP) implementing the Ultra Accelerator Link (UALink) specification, an open die-to-die and accelerator interconnect standard designed for large-scale AI infrastructure and accelerator clusters.

UALink IP enables semiconductor vendors and SoC designers to integrate UALink-compatible connectivity into AI accelerators, chiplets, switches, retimers, and networking devices. The technology targets high-bandwidth, low-latency communication between accelerators within AI training and inference systems.

The UALink ecosystem is supported by the UALink Consortium, whose founding members include AMD, Intel, Google, Meta, Microsoft, AWS, Alibaba, Apple, Cisco, Astera Labs, Hewlett Packard Enterprise, and Synopsys.

Overview

UALink was developed to address scalability limitations in AI accelerator interconnect architectures. The specification defines a high-speed interconnect fabric enabling direct communication between accelerators across large AI compute clusters.

The first generation, known as UALink 200 (UALink_200), is based on a 200 Gb/s PHY derived from IEEE P802.3dj technology. The architecture is designed to support coherent and shared-memory communication between accelerators inside AI pods containing hundreds or thousands of devices.

UALink systems typically include:

• AI accelerators or AI chiplets
• UALink switch fabrics
• High-speed PHY and SerDes interfaces
• Shared-memory transport mechanisms
• Routing and fabric management logic

The standard is intended for scale-up AI infrastructure rather than general-purpose networking.

Architecture

A UALink deployment generally consists of hosts, accelerators, and UALink switches interconnected in a scalable fabric.

Each accelerator receives a unique routing identifier within the fabric. UALink switches can interconnect up to 1024 accelerators inside a single AI pod architecture.

The protocol stack separates the physical layer from higher-level accelerator communication protocols. Accelerators may connect to host processors using technologies such as:

• PCI Express
• Compute Express Link (CXL)
• AMD Infinity Fabric
• CHI C2C
• XGMI

UALink primarily focuses on accelerator-to-accelerator communication and scalable shared-memory connectivity.

Types of UALink IP: 

UALink IP may include several categories of semiconductor IP blocks:

• UALink Controller IP: Implements protocol management, packet handling, routing, flow control, and link initialization functions required by the UALink specification.
• UALink PHY IP: Provides the high-speed physical interface layer, including serializer/deserializer (SerDes) technology, equalization, clock recovery, and signal integrity functions.
• UALink Switch IP: Implements switching fabrics enabling scalable accelerator interconnect topologies for AI clusters and AI pods.
• UALink Verification IP: Verification IP (VIP) used for protocol validation, compliance testing, simulation, and interoperability testing during chip development.
• UALink Chiplet IP: Chiplet-oriented implementations designed for die-to-die integration and heterogeneous accelerator architectures.

Applications

UALink IP is primarily targeted at:

• AI training clusters
• Large language model (LLM) infrastructure
• High-performance computing (HPC)
• AI inference servers
• Hyperscale cloud infrastructure
• Accelerator chiplets
• Scale-up AI systems

The technology is particularly relevant for systems requiring high-bandwidth shared-memory communication between many accelerators.

Industry Significance

UALink emerged as part of a broader industry effort to create open interconnect standards for AI infrastructure, reducing dependence on proprietary accelerator fabrics.

The specification competes and coexists with other interconnect technologies used in AI systems, including:

• NVLink
• Compute Express Link
• PCI Express
• Ultra Ethernet

The consortium model is intended to encourage interoperability between accelerators and infrastructure components from different vendors.

History

The UALink Consortium was formally established in 2024 to promote and standardize the technology.

The first public specification, UALink 1.0 (UALink_200), became publicly available in 2025 through an evaluation download program.

The initial specification focused on 200 Gb/s connectivity and AI scale-up architectures. Future versions are expected to increase bandwidth and expand interoperability capabilities for next-generation AI infrastructure.

Related Articles

• How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks
• Reimagining AI Infrastructure: The Power of Converged Back-end Networks

Related Products

• UALink PHY + Controller
• Simulation VIP for UALink
• UALink Subsystem
• UALink Controller
• UALink PCS IP Core

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Related Blogs

• UALink Under the Hood: Why Full-Stack Verification Wins
• Securing Scale-Up AI: Cadence’s Complete UALink Solution
• Securing UALink: Introducing Synopsys UALinkSec_200 Security Module
• Validating UPLI Protocol Across Topologies with Cadence UALink VIP
• Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP

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