英特尔和 Movellus 针对 IC 电压跌落联手开发独树一帜的解决方案

By Steven Leibson, EEJournal (June 26, 2023)

Two presentations during the same week from Intel and Movellus highlighted radically different approaches to solving voltage droop, a problem that increasingly plagues SoC designs as device geometries continue marching down the Moore’s Law curve. Intel, being a manufacturing-centric company, has developed a backside power distribution network (PDN) for its Intel 20A and 18A process nodes. Meanwhile, IP vendor Movellus has developed an extension to its digital, synthesizable clock-network IP, which allows a chip manufactured using any semiconductor process node from any foundry to sense power droop and automatically tune the on-chip clock network to eke maximum performance from the SoC’s limited power envelope.

Voltage droop arises from the IR (current-resistance) losses in a chip’s PDN. Since the first days of ICs, PDNs have been formed in the same metal layers used for routing signals to the chip’s transistors. PDN resistance increased as IC manufacturing evolved from one layer of metal to two, to a dozen, to fifteen or more, with finer and finer line widths at each step along the way. The IR drop became especially noticeable as core voltages dropped from 5 volts to 1 volt, or less. At the same time, transistor power consumption has increased as clock frequencies have risen from megahertz to gigahertz. In addition, today’s SoCs simply incorporate a lot more transistors – “billions and billions” as Carl Sagan might say – that need power. All these factors are responsible for increasing the problems associated with IR droop, which can force an IC to operate at lower-than-maximum frequencies, resulting in sub-optimum performance.

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