MIPI CSI-2
- MIPI
MIPI CSI-2
GPNPU Processor IP - 32 to 864TOPs
Designed from the ground up to address significant machine learning (ML) inference deployment challenges facing system on chip (S…
GPNPU Processor IP - 16 to 108 TOPs
Designed from the ground up to address significant machine learning (ML) inference deployment challenges facing system on chip (S…
GPNPU Processor IP - 4 to 28 TOPs
Designed from the ground up to address significant machine learning (ML) inference deployment challenges facing system on chip (S…
GPNPU Processor IP - 1 to 7 TOPs
Designed from the ground up to address significant machine learning (ML) inference deployment challenges facing system on chip (S…
Bayer Color Filter Array Interpolation Core
ASICFPGA Bayer CFA Interpolation Core: Digital cameras capture images by using a single sensor with a color filter array.
The videantis processors are the most efficient deep learning, computer vision, signal processing, and video coding processing so…
eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, i…
scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 The MIPI CSI-2 IP core is a scalab…
Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
UHD Image Signal Processing (ISP) Pipeline
The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital proc…
High Dynamic Range (HDR) Pipeline
The logiHDR is an Ultra High Definition (UHD) HDR pipeline designed for digital processing and image quality enhancements of the …
1394b FPGA Link Layer Controller
The FireCore Basic is targeted for applications with up to S3200 data transmission requirements and for designs with a non-PCI Li…
Video and Image Processing Suite
The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can u…
CoaXPress (CXP) Verification IP
CXP Verification IP implements digital interface for high speed image data transmission and intended mainly for Machine Vision ap…
Video and Vision Processing Suite
The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) funct…
ACAP HDR Image Signal Processing Framework
The ACAP HDR Image Signal Processing Framework is intended to showcase a logicBRICKS IP suite implementation of High-Dynamic Rang…
Ultrasound AFE Transceiver Chip for CMUT Transducers
The MVUS01 ultrasound transducer interface is the first generation of high-voltage (HV) ultrasound ASICs intended for portable me…
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-lo…
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the 3D look-up table (LUT) Intel® FPGA IP provides an ef…