1-56Gbps Serdes - 7nm (Multi-reference Clock)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Ultra Low Latency)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (PPA-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
A comprehensive selection of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
For the high-bandwidth applications, PCIe 3.0 PHY IP offers high-performance, multi-lane capabilities, and low-power design.
PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm
The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design.
112G-XSR Pam4 for TSMC 7nm FinFET CMOS
Accelerating multi-die, multi-chip SoC designs The Cadence® 112Gbps Extra Short Reach (XSR) SerDes IP for TSMC 7nm consists of ei…
SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm)
M31 Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
Cadence 32G NRZ multi-protocol PHY The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 7nm FinFET is a high-perf…
your custom Switch Fabric, AI, or HPC ASIC with Credo’s SerDes IP.
Accelerates AI and Hyperscale Data Center Applications The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach…
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for d…
TSMC CLN7FFLVT 7nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a architecture using high-speed digital and analog circuits that offers exceptional performance, f…
TSMC CLN7FF 7nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a architecture using high-speed digital and analog circuits that offers exceptional performance, f…
TSMC CLN7FFLVT 7nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN7FFLVT 7nm Clock Generator PLL - 600MHz-3000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN7FFLVT 7nm Clock Generator PLL - 1200MHz-6000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN7FF 7nm Clock Generator PLL - 200MHz-1000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.