PCIe Gen 4 - Enables high-speed verification, error handling, and protocol compliance
PCIe Gen 4 Verification IP ensures efficient, high-speed signaling, protocol conformance, error handling, and system interoperabi…
PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification.
10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
Low-power, long-reach, multi-protocol PHY for PCIe 4.0 The Cadence® 10Gbps multi-protocol PHY IP provides a flexible PHY IP that …
VIP for Compute Express Link (CXL)
Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be u…
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…
PCI Express to AMBA 4 AXI/3 AXI Bridge
The IP for PCI Express® to ARM® AMBA® 3 AXI/4 AXI Bridge enables designers who use the AMBA 3 AXI or 4 AXI interconnect on-chip b…
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
SerDes requirements for system-on-chip (SoC) designs are becoming increasingly demanding and must support increasing numbers of p…
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…
Low Power PCIe Gen3 PHY on TSMC CLN16FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe Gen3 PHY on TSMC CLN12FFC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and aut…
The PCIe Switch Verification IP provides an effective & efficient way to verify the components interfacing with the PCIe Switch i…
PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen5 SERDES PHY on Samsung 8LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen4 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).