USB 4.0 - Enables fast data transfer, efficient power delivery, and connectivity
USB 4.0 is the third major revision of the USB standard, offering data transfer speeds up to 20 Gbps via dual-lane operation.
USB 4.0 Verification IP provides a smart way to verify the USB 4.0 component of a SOC or a ASIC.
USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the process …
The USB4 Verification IP provides an effective & efficient way to verify the components interfacing with USB4 interface of an IP …
USB 4.0 Retimer Verification IP
The USB4 Verification IP with Retimer provides an effective & efficient way to verify the components interfacing with USB4 interf…
The USB4 Verification IP with HUB provides an effective & efficient way to verify the components interfacing with USB4 interface …
Accelerated confidence in simulation-based verification of RTL designs with USB interfaces: UCM2, USB3.1, USB3.2, USB-C, Other US…
USB4.0 router, Certified USB 5G/10G and 20G Device controller
USB 5G,10G, 20G and 4.0 Device router controller is a configurable core and implements the USB device functionality and can be in…
The Synopsys SuperSpeed USB IP solution is implemented in hundreds of designs and shipped in millions of units.
The vendor provides designers with configurable USB4 Controller and Router IP.
YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstr…
The USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF).
USB 2.0 picoPHY - TSMC 40LP, OTG
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
IP
USB 3.0 OTG PHY IP, UMC 40nm LP process
USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process.
USB 3.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process
Crystal-less USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process.
USB 2.0 picoPHY in GF (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
USB 2.0 picoPHY in UMC (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
USB 2.0 picoPHY in TSMC (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a physical (PHY) layer IP solution, designed for low power mobile and consum…
USB 3.0 PHY IP, Silicon Proven in TSMC 40LP
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.