Vendor: Logic Design Solutions Category: SATA Controller

Xilinx Ultra Scale Plus SATA HOST IP

The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4…

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Overview

The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_HOST_GTHE4 IP is compliant with Serial ATA III specification and signaling rate is 6Gbs. The LDS_SATA3_HOST_GTHE4 IP is fully synchronous with system frequency (Clock_sys) at 150MHz in case of 6Gbs speed selection. The source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.

Key features

  • Physical Layer features
    • Detect OOB and COMWAKE
    • Detect the K28.5 comma character and provides a 32 bit parallel output
    • Power management mode handled by state machine (shared between Phy and Link layer)
    • Provides error indication to upper layers
    • 8b/10b encoding and decoding in Xilinx GTHE4
    • 6Gbs Speed
  • Link Layer features
    • Scrambling of tx data and descrambling of rx data
    • CRC 32 calculation and check
    • Report transmission status and error to Transport Layer
    • Enable BIST loopback and pattern generation modes
    • Auto inserted hold primitive to avoid FIFO overflow and underflow
    • Partial and slumber power management modes
    • CONT primitive management in receive and transmit
    • The interface between the link layer and the transport layer is 32-bit wide
  • Transport Layer features
    • 48-bits sector address
    • Programmed IO (PIO) and DMA modes
    • Support BIST FIS transmission and reception
    • Automatic error FIS retry capability
    • Implement Shadow Registers and SATA SuperSet registers
    • Simple synchronous CPU and DMA Interface for data transfers including DMA hold-off capability
    • DMA interface can be connected easily to memory space or FIFOs (FIFO interface provided)
    • Support DMA Abort primitive
    • NCQ Support.

Block Diagram

LDS SATA3 HOST GTHE4 block diagram

Applications

  • Embedded Recorder

What’s Included?

  • Source Code
  • Encrypted Code

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
LDS SATA3 HOST GTHE4
Vendor
Logic Design Solutions

Provider

Logic Design Solutions
HQ: FRANCE
Logic Design Solutions is an FPGA Design and Intellectual Property (IP) company that provides Design Services, IP (cores) and DO254 methodology to FPGA customers. We engage ourself to be your high standard quality solutions provider for FPGA cores and Design Services.
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Frequently asked questions about SATA Controller IP

What is Xilinx Ultra Scale Plus SATA HOST IP?

Xilinx Ultra Scale Plus SATA HOST IP is a SATA Controller IP core from Logic Design Solutions listed on Semi IP Hub.

How should engineers evaluate this SATA Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SATA Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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