Vendor: Pico Semiconductor, Inc. Category: PLL

Wide range PLL operating from 135MHz to 945MHz (90nm UMC)

PSIWRP_U9 is a wide range PLL with the VCO operating from 175MHz to 945MHz.

Overview

PSIWRP_U9 is a wide range PLL with the VCO operating from 175MHz to 945MHz. PSIWRP_U9 can be used for a wide range of applications.

Key features

  • A wide range PLL for a wide range of applications
  • Output frequencies 175-945MHz.
  • Reference clock 25-135MHz.
  • 2 power supplies, 1V and 1.8V
  • UMC 90nm SP

Silicon Options

Foundry Node Process Maturity
UMC 90nm SP

Specifications

Identity

Part Number
PSIWRP_U9
Vendor
Pico Semiconductor, Inc.

Provider

Pico Semiconductor, Inc.
HQ: USA
Pico Semiconductor is a premier IP design service center. With its core expertise in the area of high speed communication, Pico semiconductor provides high performance and cost effective IP's for networking applications.

Learn more about PLL IP core

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This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Wide range PLL operating from 135MHz to 945MHz (90nm UMC)?

Wide range PLL operating from 135MHz to 945MHz (90nm UMC) is a PLL IP core from Pico Semiconductor, Inc. listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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