Viterbi decoder (tail-biting)

The CMS0008 Viterbi Decoder core implements Viterbi’s algorithm for maximum likelihood decoding of non-feedback convolutional codes.

The basic 1/2 rate convolutional encoder and decoder are shown above. For each input bit, two encoded bits are produced. The rate can be increased to 2/3, 3/4, 5/6, or 7/8 by non transmission (puncture) of certain bits. Punctured codes lose coding gain as the redundant content decreases.

The encoded X and Y bits are transmitted through a noisy channel. The received X and Y values are measured then presented as soft decision values to the decoder.

Burst-Mode Operation

Convolutional codes are fundamentally continuous processes and their use in burst-mode systems is problematic.

Many burst mode systems specify the use of known start- and end-states (typically zero) to correctly terminate the discontinuous data stream. However this requires insertion of non-payload termination symbols into the data stream, consuming valuable bandwidth.

A description of the processing steps follows: State Metric Unit. This block maintains a measure of probability for each possible encoder state. As each soft pair is processed, the SMU produces the most likely received data bit for each state (the Branch Data vector).

Traceback Unit. This block provides a history of most likely state transitions. This allows traceback from any current state to ever more likely predecessor states.

After a certain depth the optimum state becomes known and traceback from this point produces reliable data. The required minimum traceback depth depends on the code parameters, puncture rate and soft-decision width. The alternative tail-biting strategy places data in the termination symbols, increasing the payload size at the cost of some additional decoder complexity.

While the additional complexity might seem daunting, the actual cost penalty is not high. Our tail-biting decoder provides comparable coding gain and group delay to typical zero-terminated decoders, with a moderate increase in gate count.

• Advanced Tail-Biting Architecture yields high coding gain and low delay.
• Synthesis configurable code generator coefficients and constraint length, soft-decision width and codeblock size.
• User-defined puncture patterns.
• Flexible memory architecture suitable for FPGA or ASIC

• Native rate 1/2 code with user-defined puncture
• Programmable constraint length and generator coefficients
• Zero latency between code blocks
• Fixed code block size
• Coding gain and group delay comparable to typical continuous-mode designs