Vendor: Techno Mathematical Co., Ltd. Category: Video Processing

Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)

TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-…

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Overview

TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS).
The logic gate count and internal memory capacity are optimized to reduce cost and power consumption.

Key features

  • JPEG XS (ISO/IEC21122-1) specifications
    • Compliant with the "JPEG XS" standard standardized in 2019
  • Visually LossLess compression
    • Visually lossless due to the effect of mezzanine compression
  • Ultra Low latency
    • Delay from input to output of the order of a few lines
    • Less than 1ms delay using high-speed transmission lines
  • Various image formats supported
    • RGB, YCbCr 4:4:4/4:2:2/4:0:0, 8/10/12 bit
  • Configurable compression ratio
    • 1/2 to 1/10 compression ration in Byte unit
    • Constant Bit Rate method controlled per frame

Benefits

  • Compression format
    • JPEG XS (ISO/IEC21122-1)
  • Supported profiles: Light 422.10 , Light444.12 , Main422.10 , Main444.12 , High444.12
  • Compression throughput
    • 4pixel/clock
  • Image size (width x height)
    • 32 x 4 pixels to 8192 x 4320 pixels (changeable on request)
  • Image formats and bit depth
    • format : RGB, YCbCr 4:4:4/4:2:2/4:0:0 , bit depth : 8/10/12 bit
  • Image data, compressed data interface
    • AXI4-Stream , image data : 144bit/clk , compressed data 128bit/clk

Applications

  • Remote controlling and self driving vehicles using camera images such as: drones, robots, automobiles, infrastructure inspection machines, etc. ?High-resolution VR/AR equipment
  • Game contents
  • High-quality content streaming

What’s Included?

  • Encrypted RTL
  • Datasheets
  • Verification environment
  • Synthesis constraint
  • Bit accurate model

Specifications

Identity

Part Number
JPEG XS Encoder RTL Core
Vendor
Techno Mathematical Co., Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Techno Mathematical Co., Ltd.
HQ: Japan
"DMNA" is our proprietary algorithm. We have been developing systems and solutions based on our core compression technology, which has been cultivated through our high quality software and hardware development technology using "DMNA". We will continue to contribute to the realization of a prosperous society through the resolution of our customers' IT issues.
Contact Techno Mathematical Co., Ltd.

Learn more about Video Processing IP core

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Frequently asked questions about Video Processing IP

What is Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)?

Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS) is a Video Processing IP core from Techno Mathematical Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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